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| author | Eric Nelson <eric@nelint.com> | 2016-10-30 16:33:47 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-11-29 16:39:58 +0100 |
| commit | b33f74ead4dfd1ec0b500dc3d1cfef0e308b45c3 (patch) | |
| tree | 81f90fbf651d0892767e820aae05c5dbd719161e /configs/novena_defconfig | |
| parent | c8c35155082d11deb7a2f9ccb99b11216cbd9d55 (diff) | |
| download | u-boot-imx-b33f74ead4dfd1ec0b500dc3d1cfef0e308b45c3.zip u-boot-imx-b33f74ead4dfd1ec0b500dc3d1cfef0e308b45c3.tar.gz u-boot-imx-b33f74ead4dfd1ec0b500dc3d1cfef0e308b45c3.tar.bz2 | |
mx6: ddr: allow 32 cycles for DQS gating calibration
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.
Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'configs/novena_defconfig')
0 files changed, 0 insertions, 0 deletions