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authorVasili Galka <vvv444@gmail.com>2014-03-09 15:56:52 +0200
committerTom Rini <trini@ti.com>2014-03-12 16:22:12 -0400
commitce6889a9978822172c50c92744f0ff11138e3e37 (patch)
tree2023de2263b434a7b32b4b3b45e859e50523acc8 /config.mk
parentd73f38f7ba4d8a6309b4c35830e46935c4cd6a55 (diff)
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drivers/spi/omap3: Bug fix of premature write transfer completion
The logic determining SPI "write" transfer completion was faulty. At certain conditions (e.g. slow SPI clock freq) the transfers were interrupted before completion. Both EOT and TXS flags of channel status registeer shall be checked to ensure that all data was transferred. Tested on AM3359 chip. Signed-off-by: Vasili Galka <vasili@visionmap.com>
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