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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2013-01-30 11:19:17 +0000
committerStefano Babic <sbabic@denx.de>2013-02-12 13:52:31 +0100
commitb42b5b7a243ab3923fd80ab03f950f036b6e1329 (patch)
tree2dec05cd0a9861dd8732da17cc05bc843c2c7765 /config.mk
parent1791b1f97f71bb4f110ca851ab10479640b7bc05 (diff)
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imx: mx6q DDR3 init: Fix MR0.PPD
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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