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authorTimur Tabi <timur@freescale.com>2011-04-01 13:19:36 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-04-28 22:09:23 -0500
commitda30b9fd97f031a6b6863359f3d4c6633e5c7035 (patch)
tree8193ca2746ebc44306440f5e203f954e95d88586 /common
parent82c9dfdc20b1bf86e732e61e7230cfa7c933247f (diff)
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powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005
SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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