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author | stroese <stroese> | 2004-12-16 17:42:39 +0000 |
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committer | stroese <stroese> | 2004-12-16 17:42:39 +0000 |
commit | 4aaf29b2f53386b267d8f59891b822ea65c48786 (patch) | |
tree | dcb7d8f67228fbcef0dacf017fbd317a1a922901 /common | |
parent | fa838874cf29a18ce11371c048358f683c74ff0e (diff) | |
download | u-boot-imx-4aaf29b2f53386b267d8f59891b822ea65c48786.zip u-boot-imx-4aaf29b2f53386b267d8f59891b822ea65c48786.tar.gz u-boot-imx-4aaf29b2f53386b267d8f59891b822ea65c48786.tar.bz2 |
memory commands "mdc" and "mwc" added for cyclic read/write
Diffstat (limited to 'common')
-rw-r--r-- | common/cmd_mem.c | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/common/cmd_mem.c b/common/cmd_mem.c index b95421a..bafb1d6 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -253,6 +253,66 @@ int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } +#ifdef CONFIG_MX_CYCLIC +int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + ulong count; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + count = simple_strtoul(argv[3], NULL, 10); + + for (;;) { + do_mem_md (NULL, 0, 3, argv); + + /* delay for <count> ms... */ + for (i=0; i<count; i++) + udelay (1000); + + /* check for ctrl-c to abort... */ + if (ctrlc()) { + puts("Abort\n"); + return 0; + } + } + + return 0; +} + +int do_mem_mwc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + ulong count; + + if (argc < 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + count = simple_strtoul(argv[3], NULL, 10); + + for (;;) { + do_mem_mw (NULL, 0, 3, argv); + + /* delay for <count> ms... */ + for (i=0; i<count; i++) + udelay (1000); + + /* check for ctrl-c to abort... */ + if (ctrlc()) { + puts("Abort\n"); + return 0; + } + } + + return 0; +} +#endif /* CONFIG_MX_CYCLIC */ + int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong addr1, addr2, count, ngood; @@ -1214,5 +1274,19 @@ U_BOOT_CMD( " - simple RAM read/write test\n" ); +#ifdef CONFIG_MX_CYCLIC +U_BOOT_CMD( + mdc, 4, 1, do_mem_mdc, + "mdc - memory display cyclic\n", + "[.b, .w, .l] address count delay(ms)\n - memory display cyclic\n" +); + +U_BOOT_CMD( + mwc, 4, 1, do_mem_mwc, + "mwc - memory write cyclic\n", + "[.b, .w, .l] address value delay(ms)\n - memory write cyclic\n" +); +#endif /* CONFIG_MX_CYCLIC */ + #endif #endif /* CFG_CMD_MEMORY */ |