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authorSRICHARAN R <r.sricharan@ti.com>2013-11-08 17:40:38 +0530
committerTom Rini <trini@ti.com>2013-12-04 08:12:08 -0500
commit54d022e76c42d824315e28ea06c89c2452f98861 (patch)
tree7fd2255daf8be37b1a535c75358953fc7f4647a5 /common
parent6c70935d7525a4b2b144b49457d2bae85f1d111a (diff)
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ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039
When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: Sricharan R <r.sricharan@ti.com>
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