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| author | Sonic Zhang <sonic.zhang@analog.com> | 2012-08-16 11:56:14 +0800 |
|---|---|---|
| committer | sonic <sonic@sonic-linuxvm.(none)> | 2013-03-04 13:42:06 +0800 |
| commit | a2979dcdbeb39a01dc888090d2c736c2ad3f548d (patch) | |
| tree | a682537c30714af45a998e2c3cedbe495de05e52 /common | |
| parent | 3ead92c571e7e17ca1c525c0fcd40e58901c5655 (diff) | |
| download | u-boot-imx-a2979dcdbeb39a01dc888090d2c736c2ad3f548d.zip u-boot-imx-a2979dcdbeb39a01dc888090d2c736c2ad3f548d.tar.gz u-boot-imx-a2979dcdbeb39a01dc888090d2c736c2ad3f548d.tar.bz2 | |
blackfin: bf60x: Port blackfin core architecture code to boot on bf60x.
Set up clocks, DDR controller, Nor flash controller, reboot,
serial port. Add new SPI boot modes.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Diffstat (limited to 'common')
| -rw-r--r-- | common/cmd_reginfo.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 08a6563..b591bd3 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -191,7 +191,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, #elif defined(CONFIG_BLACKFIN) puts("\nSystem Configuration registers\n"); - +#ifndef __ADSPBF60x__ puts("\nPLL Registers\n"); printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); @@ -227,7 +227,24 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); # endif +#else + puts("\nCGU Registers\n"); + printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n", + bfin_read_CGU_DIV(), bfin_read_CGU_CTL()); + printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n", + bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL()); + puts("\nSMC DDR Registers\n"); + printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n", + bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0()); + printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n", + bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2()); + printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n", + bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1()); + printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n", + bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT()); + printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL()); +#endif #endif /* CONFIG_BLACKFIN */ return 0; |