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| author | wdenk <wdenk> | 2004-02-27 00:07:27 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-02-27 00:07:27 +0000 |
| commit | 11dadd547c08a3480ea153482e99c6ae70b73415 (patch) | |
| tree | 2386e4f325ab15e52cfadcb34c3d8ba8e36fb977 /common/virtex2.c | |
| parent | 80885a9d526b6b9666500d17ec7941b9dad8de44 (diff) | |
| download | u-boot-imx-11dadd547c08a3480ea153482e99c6ae70b73415.zip u-boot-imx-11dadd547c08a3480ea153482e99c6ae70b73415.tar.gz u-boot-imx-11dadd547c08a3480ea153482e99c6ae70b73415.tar.bz2 | |
* Patch by Steven Scholz, 25 Feb 2004:
- Timeouts in FPGA code should be based on CFG_HZ
- Minor cleanup in code for Altera FPGA ACEX1K
* Patch by Steven Scholz, 25 Feb 2004:
Changed "Directory Hierarchy" section in README
* Patch by Masami Komiya, 25 Feb 2004:
Reduce copy count in nfs_read_reply() of NFS code
Diffstat (limited to 'common/virtex2.c')
| -rw-r--r-- | common/virtex2.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/common/virtex2.c b/common/virtex2.c index b519be9..bb44eaa 100644 --- a/common/virtex2.c +++ b/common/virtex2.c @@ -80,7 +80,7 @@ * an XC2V1000, if anyone can ever get ahold of one. */ #ifndef CFG_FPGA_WAIT_INIT -#define CFG_FPGA_WAIT_INIT 500 /* time in milliseconds */ +#define CFG_FPGA_WAIT_INIT CFG_HZ/2 /* 500 ms */ #endif /* @@ -89,14 +89,14 @@ * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ #ifndef CFG_FPGA_WAIT_BUSY -#define CFG_FPGA_WAIT_BUSY 5 /* time in milliseconds */ +#define CFG_FPGA_WAIT_BUSY CFG_HZ/200 /* 5 ms*/ #endif /* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ #ifndef CFG_FPGA_WAIT_CONFIG -#define CFG_FPGA_WAIT_CONFIG 200 /* time in milliseconds */ +#define CFG_FPGA_WAIT_CONFIG CFG_HZ/5 /* 200 ms */ #endif static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); |