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authorThierry Reding <treding@nvidia.com>2013-07-18 12:13:40 -0700
committerTom Warren <twarren@nvidia.com>2013-08-19 15:31:37 -0700
commit0d79f4f490352f6e1500cdd12a3b0e8b17265bde (patch)
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parent9ed887caecb9ecb0c68773a1870d143b9f28d3da (diff)
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ARM: tegra: Make cache line size SoC specific
Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Signed-off-by: Thierry Reding <treding@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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