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authorYork Sun <yorksun@freescale.com>2013-03-25 07:40:07 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-24 16:54:11 -0500
commitf69814397e7efaf0b2bfa3c83425c906ce6b50f4 (patch)
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powerpc/chassis2: Change core numbering scheme
To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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