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authorwdenk <wdenk>2002-12-07 00:20:59 +0000
committerwdenk <wdenk>2002-12-07 00:20:59 +0000
commit7c7a23bd5a0bc149d2edd665ec46381726b24e0c (patch)
treed859f82ea2561180db2ffd7569f0b9007d710769 /common/cmd_pci.c
parent1f53a41603b9093c59741f4208fef0ab3790d6ce (diff)
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* Patch by Hans-Joerg Frieden, 06 Dec 2002
Fix misc problems with AmigaOne support * Patch by Chris Hallinan, 3 Dec 2002: minor cleanup to the MPC8245 EPIC driver * Patch by Pierre Aubert , 28 Nov 2002 Add support for external (SIU) interrupts on MPC8xx * Patch by Pierre Aubert , 28 Nov 2002 Fix nested syscalls bug in standalone applications * Patch by David Müller, 27 Nov 2002: fix output of "pciinfo" command for CardBus bridge devices. * Fix bug in TQM8260 board detection - boards got stuck when board ID was not readable
Diffstat (limited to 'common/cmd_pci.c')
-rw-r--r--common/cmd_pci.c68
1 files changed, 53 insertions, 15 deletions
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index 300ac02..5a3b557 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -205,9 +205,27 @@ void pci_header_show(pci_dev_t dev)
PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
- PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
- if (header_type & 0x01) { /* PCI-to-PCI bridge */
+ switch (header_type & 0x03) {
+ case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
+ PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
+ PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
+ PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
+ PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
+ PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
+ PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
+ PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
+ PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
+ PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
+ PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
+ PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
+ PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
+ PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
+ break;
+
+ case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
+
+ PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
@@ -227,19 +245,39 @@ void pci_header_show(pci_dev_t dev)
PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
- } else { /* PCI device */
- PRINT(" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
- PRINT(" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
- PRINT(" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
- PRINT(" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
- PRINT(" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
- PRINT(" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
- PRINT(" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
- PRINT(" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
- PRINT(" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
- PRINT(" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
- PRINT(" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
- PRINT(" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
+ break;
+
+ case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
+
+ PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
+ PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
+ PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
+ PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
+ PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
+ PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
+ PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
+ PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
+ PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
+ PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
+ PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
+ PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
+ PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
+ PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
+ PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
+ PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
+ PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
+ PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
+ PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
+ PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
+ PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
+ PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
+ PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
+ PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
+ break;
+
+ default:
+ printf("unknown header\n");
+ break;
}
#undef PRINT