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author | Nishanth Menon <nm@ti.com> | 2015-08-13 09:51:00 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2015-08-28 12:33:13 -0400 |
commit | 76cff2b10857c86211ef60024e672ce178cb6d69 (patch) | |
tree | fdf9d2554b43cbcd5e08c0c0e51b2344a8224896 /common/cmd_onenand.c | |
parent | 03589234090db645f80896a2ee5bce98096172da (diff) | |
download | u-boot-imx-76cff2b10857c86211ef60024e672ce178cb6d69.zip u-boot-imx-76cff2b10857c86211ef60024e672ce178cb6d69.tar.gz u-boot-imx-76cff2b10857c86211ef60024e672ce178cb6d69.tar.bz2 |
ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.
Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.
NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'common/cmd_onenand.c')
0 files changed, 0 insertions, 0 deletions