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authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:11 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:16 -0500
commit9a653a9810160351ba1930ec55eae37c1a492b78 (patch)
tree74be1c446c2cdd731408bad59c553300371fab4d /common/cmd_onenand.c
parent2f1712b275af3ed960b92cd1ed9b99d23c4919a5 (diff)
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powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2
Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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