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| author | Ruchika Gupta <ruchika.gupta@freescale.com> | 2010-12-15 17:02:08 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-10-03 08:52:14 -0500 |
| commit | 7065b7d466dfc4fbfa8a608cf21206efe59c01d9 (patch) | |
| tree | b6c9d32bc4be7a818a4b594b9af7e1997ffb28e8 /boards.cfg | |
| parent | 2f439e805e945b410b0043db82f9666eb03914ba (diff) | |
| download | u-boot-imx-7065b7d466dfc4fbfa8a608cf21206efe59c01d9.zip u-boot-imx-7065b7d466dfc4fbfa8a608cf21206efe59c01d9.tar.gz u-boot-imx-7065b7d466dfc4fbfa8a608cf21206efe59c01d9.tar.bz2 | |
powerpc/p4080: Add support for secure boot flow
Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
(Please note that ISBC expects all these addresses, images to be
validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
at 0xcffffffc.
Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
(The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
created by PBL/configuration word within 0 - 3.5G memory range. The
u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
PBL/configuration word after switch to AS = 1
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: Wood Scott-B07421 <B07421@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'boards.cfg')
| -rw-r--r-- | boards.cfg | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -670,6 +670,7 @@ P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freesca P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P4080DS powerpc mpc85xx corenet_ds freescale P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 |