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| author | Becky Bruce <beckyb@kernel.crashing.org> | 2010-12-17 17:17:54 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:19 -0600 |
| commit | 5b297d1a4269308a459d123cfb91a3c91f57337c (patch) | |
| tree | 39edc598eb5f0d869102bdf1f9f5d81efb818d05 /board | |
| parent | 058d7dc7ba28a45ae6bb7f6ef12b978b31584406 (diff) | |
| download | u-boot-imx-5b297d1a4269308a459d123cfb91a3c91f57337c.zip u-boot-imx-5b297d1a4269308a459d123cfb91a3c91f57337c.tar.gz u-boot-imx-5b297d1a4269308a459d123cfb91a3c91f57337c.tar.bz2 | |
tqm85xx: create fixed_sdram() to do sdram setup
Also, change this code to use phys_size_t instead of long int.
Using common naming for this function will enable us to use the common
initdram() for 85xx going forward. Other than the type change,
this is just a code rearrange.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/tqc/tqm85xx/sdram.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 503c5e5..260cd1c 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -65,6 +65,7 @@ sdram_conf_t ddr_cs_conf[] = { #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) int cas_latency (void); +static phys_size_t sdram_setup(int); /* * Autodetect onboard DDR SDRAM on 85xx platforms @@ -73,7 +74,26 @@ int cas_latency (void); * so this should be extended for other future boards * using this routine! */ -long int sdram_setup (int casl) +phys_size_t fixed_sdram(void) +{ + int casl = 0; + phys_size_t dram_size = 0; + + casl = cas_latency(); + dram_size = sdram_setup(casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + printf("Problem with CAS lantency, using default CL %d/10!\n", + CONFIG_DDR_DEFAULT_CL); + dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); + puts(" "); + } + return dram_size; +} + +static phys_size_t sdram_setup(int casl) { int i; volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); @@ -376,8 +396,7 @@ long int sdram_setup (int casl) phys_size_t initdram (int board_type) { - long dram_size = 0; - int casl; + phys_size_t dram_size = 0; #if defined(CONFIG_DDR_DLL) /* @@ -407,17 +426,7 @@ phys_size_t initdram (int board_type) } #endif - casl = cas_latency (); - dram_size = sdram_setup (casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - printf ("Problem with CAS lantency, using default CL %d/10!\n", - CONFIG_DDR_DEFAULT_CL); - dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL); - puts (" "); - } + dram_size = fixed_sdram(); return dram_size; } |