Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  SMDKV310: Fix incorrect conditional compilation for MIU linear mapping
  SMDKV310: CPU fequency and mmc_pre_ratio modified
  armv7: Add support for ST-Ericsson U8500 href platform
  I2C: Add driver for ST-Ericsson U8500 i2c
  armv7: Add ST-Ericsson u8500 arch
  Kirkwood: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT
  ARMV7: Vexpress: Add missing MMC header
  arm/km: update mgcoge3un board support
  mvgbe: enable configurability of PORT_SERIAL_CONTROL_VALUE
  arm/km: rename mgcoge2un to mgcoge3un
  arm/km: add second serial interface for kirkwood
  arm/km: disable ls (through jffs2 support)
  arm/km: introduce bootcount env variable and clean km_arm
  arm/km: move CONFIG_EXTRA_ENV_SETTINGS from board to km_arm file
  arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h
  ARMV7: MMC SPL Boot support for SMDKV310 board
  ARMV7: Add support for Samsung SMDKV310 Board
  S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)
  S5P: add set_mmc_clk for external clock control
  S5PC2XX: Support the cpu revision
  S5P:SROM config code moved to s5p-common directory
  Add _end for the end of u-boot image for SMDK6400
  MMC S5P: Fix typo
  S5P: GPIO Macro Values Corrected.
  SMDK2410: various cleanup/code style fixes
  SMDK2410: use the CFI driver (and remove the old one)
  SMDK2410: remove unneeded config.mk
  SMDK2410: activate ARM relocation feature
  BeagleBoard: fixed typo in typecast
  mvsata: issue hard reset on initialization
  VCMA9: use ARM relocation feature to fix build error
  MX31: drop warnings due to missing prototype for mxc_watchdog_reset()
  MX5: drop config.mk from efikamx board
  MX31: Make get_reset_cause() static and drop unreachable code
  MX53: Remove CONFIG_SYS_BOOTMAPSZ from mx53 config files.
  MX53: Handle silicon revision 2.1 case
  mx5: board: code clean up for checkboard code
  MX51: vision2: Fix build for vision2 board.
  MX51: vision: Let video mode struct be independant of watchdog.
  MX53: Add initial support for MX53SMD board.
  MX53: support for freescale MX53LOCO board
  mx5: Fix CONFIG_OF_LIBFDT redefined warning
  mx5: Remove unnecessary CONFIG_SYS_BOOTMAPSZ definition
  mx31pdk: Clean up mx31pdk.h file

28 files changed, 3291 insertions, 664 deletions

diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c
index 3566b95..6e5884b 100644
--- a/board/armltd/vexpress/ca9x4_ct_vxp.c
+++ b/board/armltd/vexpress/ca9x4_ct_vxp.c
@@ -38,6 +38,7 @@
 #include <asm/arch/systimer.h>
 #include <asm/arch/sysctrl.h>
 #include <asm/arch/wdt.h>
+#include "../drivers/mmc/arm_pl180_mmci.h"
 
 static ulong timestamp;
 static ulong lastdec;
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index f735260..16be532 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -643,47 +643,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	u32 system_rev = get_cpu_rev();
-	u32 cause;
-	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
-
-	puts("Board: Efika MX ");
-
-	switch (system_rev & 0xff) {
-	case CHIP_REV_3_0:
-		puts("3.0 [");
-		break;
-	case CHIP_REV_2_5:
-		puts("2.5 [");
-		break;
-	case CHIP_REV_2_0:
-		puts("2.0 [");
-		break;
-	case CHIP_REV_1_1:
-		puts("1.1 [");
-		break;
-	case CHIP_REV_1_0:
-	default:
-		puts("1.0 [");
-		break;
-	}
-
-	cause = src_regs->srsr;
-	switch (cause) {
-	case 0x0001:
-		puts("POR");
-		break;
-	case 0x0009:
-		puts("RST");
-		break;
-	case 0x0010:
-	case 0x0011:
-		puts("WDOG");
-		break;
-	default:
-		printf("unknown 0x%x", cause);
-	}
-	puts("]\n");
+	puts("Board: Efika MX\n");
 
 	return 0;
 }
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 02a765d..e2d3d74 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -431,41 +431,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board: MX51EVK ");
-
-	switch (system_rev & 0xff) {
-	case CHIP_REV_3_0:
-		puts("3.0 [");
-		break;
-	case CHIP_REV_2_5:
-		puts("2.5 [");
-		break;
-	case CHIP_REV_2_0:
-		puts("2.0 [");
-		break;
-	case CHIP_REV_1_1:
-		puts("1.1 [");
-		break;
-	case CHIP_REV_1_0:
-	default:
-		puts("1.0 [");
-		break;
-	}
+	puts("Board: MX51EVK\n");
 
-	switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
-	case 0x0001:
-		puts("POR");
-		break;
-	case 0x0009:
-		puts("RST");
-		break;
-	case 0x0010:
-	case 0x0011:
-		puts("WDOG");
-		break;
-	default:
-		puts("unknown");
-	}
-	puts("]\n");
 	return 0;
 }
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index e71701b..a89aa25 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -372,26 +372,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	u32 cause;
-	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+	puts("Board: MX53EVK\n");
 
-	puts("Board: MX53EVK [");
-
-	cause = src_regs->srsr;
-	switch (cause) {
-	case 0x0001:
-		printf("POR");
-		break;
-	case 0x0009:
-		printf("RST");
-		break;
-	case 0x0010:
-	case 0x0011:
-		printf("WDOG");
-		break;
-	default:
-		printf("unknown");
-	}
-	printf("]\n");
 	return 0;
 }
diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile
new file mode 100644
index 0000000..2088a48
--- /dev/null
+++ b/board/freescale/mx53loco/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx53loco.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
new file mode 100644
index 0000000..ce9c8fc
--- /dev/null
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -0,0 +1,96 @@
+# Copyright (C) 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM	sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x04000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
new file mode 100644
index 0000000..d032428
--- /dev/null
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/clock.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <mxc_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int dram_init(void)
+{
+	u32 size1, size2;
+
+	size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	gd->ram_size = size1 + size2;
+
+	return 0;
+}
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+static void setup_iomux_uart(void)
+{
+	/* UART1 RXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+	/* UART1 TXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+	/* FEC RXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	 /* FEC TXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC CRS */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+	{MMC_SDHC3_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		*cd = mxc_gpio_get(77); /*GPIO3_13*/
+	else
+		*cd = mxc_gpio_get(75); /*GPIO3_11*/
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA0,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA1,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA2,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA3,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_EIM_DA13,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			break;
+		case 1:
+			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_IORDY,
+						IOMUX_CONFIG_ALT2);
+			mxc_request_iomux(MX53_PIN_ATA_DATA8,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA9,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA10,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA11,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA0,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA1,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA2,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_ATA_DATA3,
+						IOMUX_CONFIG_ALT4);
+			mxc_request_iomux(MX53_PIN_EIM_DA11,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_MX53_LOCO;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX53 LOCO\n");
+
+	return 0;
+}
diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile
new file mode 100644
index 0000000..ee60f34
--- /dev/null
+++ b/board/freescale/mx53smd/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx53smd.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
new file mode 100644
index 0000000..0f298ab
--- /dev/null
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -0,0 +1,96 @@
+#
+# (C) Copyright 2009
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM	sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x04000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901C 0x00000000
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
new file mode 100644
index 0000000..f3c433f
--- /dev/null
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <mxc_gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int dram_init(void)
+{
+	u32 size1, size2;
+
+	size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	gd->ram_size = size1 + size2;
+
+	return 0;
+}
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+static void setup_iomux_uart(void)
+{
+	/* UART1 RXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+	/* UART1 TXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+	/* FEC RXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	 /* FEC TXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+
+	/* FEC CRS */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{MMC_SDHC1_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	*cd = mxc_gpio_get(77); /*GPIO3_13*/
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA0,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA1,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA2,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_SD1_DATA3,
+						IOMUX_CONFIG_ALT0);
+			mxc_request_iomux(MX53_PIN_EIM_DA13,
+						IOMUX_CONFIG_ALT1);
+
+			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+				PAD_CTL_DRV_HIGH);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			break;
+
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(1)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_MX53_SMD;
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX53SMD\n");
+
+	return 0;
+}
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index c772ee2..d86acc9 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -41,6 +41,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * BOCO FPGA definitions
+ */
+#define BOCO		0x10
+#define REG_CTRL_H		0x02
+#define MASK_WRL_UNITRUN	0x01
+#define MASK_RBX_PGY_PRESENT	0x40
+#define REG_IRQ_CIRQ2		0x2d
+#define MASK_RBI_DEFECT_16	0x01
+
 /* Multi-Purpose Pins Functionality configuration */
 u32 kwmpp_config[] = {
 	MPP0_NF_IO2,
@@ -102,68 +112,119 @@ u32 kwmpp_config[] = {
 	0
 };
 
+#if defined(CONFIG_MGCOGE3UN)
+/*
+ * Wait for startup OK from mgcoge3ne
+ */
+int startup_allowed(void)
+{
+	unsigned char buf;
+
+	/*
+	 * Read CIRQ16 bit (bit 0)
+	 */
+	if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
+		printf("%s: Error reading Boco\n", __func__);
+	else
+		if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
+			return 1;
+	return 0;
+}
+
+/*
+ * mgcoge3un has always ethernet present. Its connected to the 6061 switch
+ * and provides ICNev and piggy4 connections.
+ */
+int ethernet_present(void)
+{
+	return 1;
+}
+#else
 int ethernet_present(void)
 {
 	uchar	buf;
 	int	ret = 0;
 
-	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
+	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 		printf("%s: Error reading Boco\n", __func__);
 		return -1;
 	}
-	if ((buf & 0x40) == 0x40)
+	if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
 		ret = 1;
 
 	return ret;
 }
+#endif
 
 int initialize_unit_leds(void)
 {
 	/*
-	 * init the unit LEDs
-	 * per default they all are
+	 * Init the unit LEDs per default they all are
 	 * ok apart from bootstat
-	 * LED connected through BOCO
-	 * BOCO	lies at the address  0x10
-	 * LEDs are in the block CTRL_H	(addr 0x02)
-	 * BOOTSTAT LED is the first 0x01
 	 */
-	#define BOCO        0x10
-	#define CTRL_H      0x02
-	#define APPLEDMASK  0x01
 	uchar buf;
 
-	if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) {
+	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 		printf("%s: Error reading Boco\n", __func__);
 		return -1;
 	}
-	buf |= APPLEDMASK;
-	if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) {
+	buf |= MASK_WRL_UNITRUN;
+	if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 		printf("%s: Error writing Boco\n", __func__);
 		return -1;
 	}
 	return 0;
 }
 
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void set_bootcount_addr(void)
+{
+	uchar buf[32];
+	unsigned int bootcountaddr;
+	bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
+	sprintf((char *)buf, "0x%x", bootcountaddr);
+	setenv("bootcountaddr", (char *)buf);
+}
+#endif
+
 int misc_init_r(void)
 {
 	char *str;
 	int mach_type;
 
-	puts("Piggy:");
-	if (ethernet_present() == 0)
-		puts (" not");
-	puts(" present\n");
-
 	str = getenv("mach_type");
 	if (str != NULL) {
 		mach_type = simple_strtoul(str, NULL, 10);
 		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
 		gd->bd->bi_arch_number = mach_type;
 	}
+#if defined(CONFIG_MGCOGE3UN)
+	char *wait_for_ne;
+	wait_for_ne = getenv("waitforne");
+	if (wait_for_ne != NULL) {
+		if (strcmp(wait_for_ne, "true") == 0) {
+			int cnt = 0;
+			puts("NE go: ");
+			while (startup_allowed() == 0) {
+				udelay(200000);
+				cnt++;
+				if (cnt == 5)
+					puts("wait\b\b\b\b");
+				if (cnt == 10) {
+					cnt = 0;
+					puts("    \b\b\b\b");
+				}
+			}
+			puts("OK\n");
+		}
+	}
+#endif
 
 	initialize_unit_leds();
-
+	set_km_env();
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+	set_bootcount_addr();
+#endif
 	return 0;
 }
 
@@ -182,7 +243,6 @@ int board_early_init_f(void)
 	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
 	tmp = readl(KW_GPIO0_BASE + 4);
 	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
-	printf("KM: setting NAND mode\n");
 
 #if defined(CONFIG_SOFT_I2C)
 	/* init the GPIO for I2C Bitbang driver */
@@ -212,12 +272,6 @@ int board_init(void)
 	return 0;
 }
 
-int last_stage_init(void)
-{
-	set_km_env();
-	return 0;
-}
-
 #if defined(CONFIG_CMD_SF)
 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg
new file mode 100644
index 0000000..2faaf2b
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -0,0 +1,197 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2011
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222	# MPP Control 0 Register
+# bit 3-0:   MPPSel0	2, NF_IO[2]
+# bit 7-4:   MPPSel1	2, NF_IO[3]
+# bit 12-8:  MPPSel2	2, NF_IO[4]
+# bit 15-12: MPPSel3	2, NF_IO[5]
+# bit 19-16: MPPSel4	1, NF_IO[6]
+# bit 23-20: MPPSel5	1, NF_IO[7]
+# bit 27-24: MPPSel6	1, SYSRST_O
+# bit 31-28: MPPSel7	0, GPO[7]
+
+DATA 0xFFD10004 0x03303300
+
+DATA 0xFFD10008 0x00001100	# MPP Control 2 Register
+# bit 3-0:   MPPSel16	0, GPIO[16]
+# bit 7-4:   MPPSel17	0, GPIO[17]
+# bit 12-8:  MPPSel18	1, NF_IO[0]
+# bit 15-12: MPPSel19	1, NF_IO[1]
+# bit 19-16: MPPSel20	0, GPIO[20]
+# bit 23-20: MPPSel21	0, GPIO[21]
+# bit 27-24: MPPSel22	0, GPIO[22]
+# bit 31-28: MPPSel23	0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B	# IO Configuration 0 Register
+DATA 0xFFD20134 0x66666666	# L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666	# L2 RAM Timing 1 Register
+DATA 0xFFD20154 0x00000200	# CPU RAM Management Control3 Register
+DATA 0xFFD2014C 0x00001C00	# CPU RAM Management Control1 Register
+DATA 0xFFD20148 0x00000001	# CPU RAM Management Control0 Register
+
+#Dram initalization
+DATA 0xFFD01400 0x430004E0	# SDRAM Configuration Register
+# bit13-0:  0x4E0 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38543000	# DDR Controller Control Low
+# bit 3-0:  0 reserved
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302433E	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A3E	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000001	#  DDR Address Control
+# bit1-0:   01, Cs0width=x16
+# bit3-2:   00, Cs0size=2Gb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000652	#  DDR Mode
+DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd disabled
+# bit5-3:  000, required
+# bit6:    0,  DDR ODT control msb disabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add a sample stage
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00084520	# DDR2 SDRAM Timing Low
+# bit3-0  : 0000, required
+# bit7-4  : 0010, M_ODT assertion 2 cycles after read
+# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read
+# bit15-12: 0100, internal ODT assertion 4 cycles after read
+# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
+# bit31-20: 0   , required
+
+DATA 0xFFD0147c 0x00008451	# DDR2 SDRAM Timing High
+# bit3-0  : 0001, M_ODT assertion same cycle as write
+# bit7-4  : 0101, M_ODT de-assertion x cycles after write
+# bit11-8 : 0100, internal ODT assertion x cycles after write
+# bit15-12: 1000, internal ODT de-assertion x cycles after write
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F801	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit9-8:  0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
+# bit14   :1, STARTBURST ODT enabled
+# bit15   :1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+# bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/samsung/smdk2410/Makefile b/board/samsung/smdk2410/Makefile
index bda8898..0afe1e2 100644
--- a/board/samsung/smdk2410/Makefile
+++ b/board/samsung/smdk2410/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= smdk2410.o flash.o
+COBJS	:= smdk2410.o
 SOBJS	:= lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/samsung/smdk2410/config.mk b/board/samsung/smdk2410/config.mk
deleted file mode 100644
index c8d1b1f..0000000
--- a/board/samsung/smdk2410/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-#
-
-#
-# SMDK2410 has 1 bank of 64 MB DRAM
-#
-# 3000'0000 to 3400'0000
-#
-# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
-# optionally with a ramdisk at 3080'0000
-#
-# we load ourself to 33F8'0000
-#
-# download area is 3300'0000
-#
-
-
-CONFIG_SYS_TEXT_BASE = 0x33F80000
diff --git a/board/samsung/smdk2410/flash.c b/board/samsung/smdk2410/flash.c
deleted file mode 100644
index 132d752..0000000
--- a/board/samsung/smdk2410/flash.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-ulong myflush (void);
-
-
-#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
-#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-#define CMD_READ_ARRAY		0x000000F0
-#define CMD_UNLOCK1		0x000000AA
-#define CMD_UNLOCK2		0x00000055
-#define CMD_ERASE_SETUP		0x00000080
-#define CMD_ERASE_CONFIRM	0x00000030
-#define CMD_PROGRAM		0x000000A0
-#define CMD_UNLOCK_BYPASS	0x00000020
-
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
-
-#define BIT_ERASE_DONE		0x00000080
-#define BIT_RDY_MASK		0x00000080
-#define BIT_PROGRAM_ERROR	0x00000020
-#define BIT_TIMEOUT		0x80000000	/* our flag */
-
-#define READY 1
-#define ERR   2
-#define TMO   4
-
-/*-----------------------------------------------------------------------
- */
-
-ulong flash_init (void)
-{
-	int i, j;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		ulong flashbase = 0;
-
-		flash_info[i].flash_id =
-#if defined(CONFIG_AMD_LV400)
-			(AMD_MANUFACT & FLASH_VENDMASK) |
-			(AMD_ID_LV400B & FLASH_TYPEMASK);
-#elif defined(CONFIG_AMD_LV800)
-			(AMD_MANUFACT & FLASH_VENDMASK) |
-			(AMD_ID_LV800B & FLASH_TYPEMASK);
-#else
-#error "Unknown flash configured"
-#endif
-			flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-		if (i == 0)
-			flashbase = PHYS_FLASH_1;
-		else
-			panic ("configured too many flash banks!\n");
-		for (j = 0; j < flash_info[i].sector_count; j++) {
-			if (j <= 3) {
-				/* 1st one is 16 KB */
-				if (j == 0) {
-					flash_info[i].start[j] =
-						flashbase + 0;
-				}
-
-				/* 2nd and 3rd are both 8 KB */
-				if ((j == 1) || (j == 2)) {
-					flash_info[i].start[j] =
-						flashbase + 0x4000 + (j -
-								      1) *
-						0x2000;
-				}
-
-				/* 4th 32 KB */
-				if (j == 3) {
-					flash_info[i].start[j] =
-						flashbase + 0x8000;
-				}
-			} else {
-				flash_info[i].start[j] =
-					flashbase + (j - 3) * MAIN_SECT_SIZE;
-			}
-		}
-		size += flash_info[i].size;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-		       &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case (AMD_MANUFACT & FLASH_VENDMASK):
-		printf ("AMD: ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case (AMD_ID_LV400B & FLASH_TYPEMASK):
-		printf ("1x Amd29LV400BB (4Mbit)\n");
-		break;
-	case (AMD_ID_LV800B & FLASH_TYPEMASK):
-		printf ("1x Amd29LV800BB (8Mbit)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		goto Done;
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-
-      Done:;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	ushort result;
-	int iflag, cflag, prot, sect;
-	int rc = ERR_OK;
-	int chip;
-
-	/* first look for protection bits */
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return ERR_UNKNOWN_FLASH_TYPE;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		return ERR_INVAL;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) !=
-	    (AMD_MANUFACT & FLASH_VENDMASK)) {
-		return ERR_UNKNOWN_FLASH_VENDOR;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot)
-		return ERR_PROTECTED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	cflag = icache_status ();
-	icache_disable ();
-	iflag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
-		printf ("Erasing sector %2d ... ", sect);
-
-		/* arm simple, non interrupt dependent timer */
-		reset_timer_masked ();
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			vu_short *addr = (vu_short *) (info->start[sect]);
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			*addr = CMD_ERASE_CONFIRM;
-
-			/* wait until flash is ready */
-			chip = 0;
-
-			do {
-				result = *addr;
-
-				/* check timeout */
-				if (get_timer_masked () >
-				    CONFIG_SYS_FLASH_ERASE_TOUT) {
-					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-					chip = TMO;
-					break;
-				}
-
-				if (!chip
-				    && (result & 0xFFFF) & BIT_ERASE_DONE)
-					chip = READY;
-
-				if (!chip
-				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
-					chip = ERR;
-
-			} while (!chip);
-
-			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
-			if (chip == ERR) {
-				rc = ERR_PROG_ERROR;
-				goto outahere;
-			}
-			if (chip == TMO) {
-				rc = ERR_TIMOUT;
-				goto outahere;
-			}
-
-			printf ("ok.\n");
-		} else {	/* it was protected */
-
-			printf ("protected!\n");
-		}
-	}
-
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-      outahere:
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-
-	if (iflag)
-		enable_interrupts ();
-
-	if (cflag)
-		icache_enable ();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash
- */
-
-static int write_hword (flash_info_t * info, ulong dest, ushort data)
-{
-	vu_short *addr = (vu_short *) dest;
-	ushort result;
-	int rc = ERR_OK;
-	int cflag, iflag;
-	int chip;
-
-	/*
-	 * Check if Flash is (sufficiently) erased
-	 */
-	result = *addr;
-	if ((result & data) != data)
-		return ERR_NOT_ERASED;
-
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	cflag = icache_status ();
-	icache_disable ();
-	iflag = disable_interrupts ();
-
-	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
-	*addr = CMD_PROGRAM;
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked ();
-
-	/* wait until flash is ready */
-	chip = 0;
-	do {
-		result = *addr;
-
-		/* check timeout */
-		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			chip = ERR | TMO;
-			break;
-		}
-		if (!chip && ((result & 0x80) == (data & 0x80)))
-			chip = READY;
-
-		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
-			result = *addr;
-
-			if ((result & 0x80) == (data & 0x80))
-				chip = READY;
-			else
-				chip = ERR;
-		}
-
-	} while (!chip);
-
-	*addr = CMD_READ_ARRAY;
-
-	if (chip == ERR || *addr != data)
-		rc = ERR_PROG_ERROR;
-
-	if (iflag)
-		enable_interrupts ();
-
-	if (cflag)
-		icache_enable ();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	int l;
-	int i, rc;
-	ushort data;
-
-	wp = (addr & ~1);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *) cp << 8);
-		}
-		for (; i < 2 && cnt > 0; ++i) {
-			data = (data >> 8) | (*src++ << 8);
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 2; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *) cp << 8);
-		}
-
-		if ((rc = write_hword (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 2;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 2) {
-		data = *((vu_short *) src);
-		if ((rc = write_hword (info, wp, data)) != 0) {
-			return (rc);
-		}
-		src += 2;
-		wp += 2;
-		cnt -= 2;
-	}
-
-	if (cnt == 0) {
-		return ERR_OK;
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 8);
-		--cnt;
-	}
-	for (; i < 2; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *) cp << 8);
-	}
-
-	return write_hword (info, wp, data);
-}
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
index 76a24bb..e9ba922 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -3,7 +3,7 @@
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  *
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2010
  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/io.h>
 #include <asm/arch/s3c24x0_cpu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -55,7 +56,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define U_M_SDIV	0x2
 #endif
 
-static inline void delay (unsigned long loops)
+static inline void pll_delay(unsigned long loops)
 {
 	__asm__ volatile ("1:\n"
 	  "subs %0, %1, #1\n"
@@ -66,44 +67,51 @@ static inline void delay (unsigned long loops)
  * Miscellaneous platform dependent initialisations
  */
 
-int board_init (void)
+int board_early_init_f(void)
 {
 	struct s3c24x0_clock_power * const clk_power =
 					s3c24x0_get_base_clock_power();
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
 	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->locktime = 0xFFFFFF;
+	writel(0xFFFFFF, &clk_power->locktime);
 
 	/* configure MPLL */
-	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+	writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
+	       &clk_power->mpllcon);
 
 	/* some delay between MPLL and UPLL */
-	delay (4000);
+	pll_delay(4000);
 
 	/* configure UPLL */
-	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
+	       &clk_power->upllcon);
 
 	/* some delay between MPLL and UPLL */
-	delay (8000);
+	pll_delay(8000);
 
 	/* set up the I/O ports */
-	gpio->gpacon = 0x007FFFFF;
-	gpio->gpbcon = 0x00044555;
-	gpio->gpbup = 0x000007FF;
-	gpio->gpccon = 0xAAAAAAAA;
-	gpio->gpcup = 0x0000FFFF;
-	gpio->gpdcon = 0xAAAAAAAA;
-	gpio->gpdup = 0x0000FFFF;
-	gpio->gpecon = 0xAAAAAAAA;
-	gpio->gpeup = 0x0000FFFF;
-	gpio->gpfcon = 0x000055AA;
-	gpio->gpfup = 0x000000FF;
-	gpio->gpgcon = 0xFF95FFBA;
-	gpio->gpgup = 0x0000FFFF;
-	gpio->gphcon = 0x002AFAAA;
-	gpio->gphup = 0x000007FF;
+	writel(0x007FFFFF, &gpio->gpacon);
+	writel(0x00044555, &gpio->gpbcon);
+	writel(0x000007FF, &gpio->gpbup);
+	writel(0xAAAAAAAA, &gpio->gpccon);
+	writel(0x0000FFFF, &gpio->gpcup);
+	writel(0xAAAAAAAA, &gpio->gpdcon);
+	writel(0x0000FFFF, &gpio->gpdup);
+	writel(0xAAAAAAAA, &gpio->gpecon);
+	writel(0x0000FFFF, &gpio->gpeup);
+	writel(0x000055AA, &gpio->gpfcon);
+	writel(0x000000FF, &gpio->gpfup);
+	writel(0xFF95FFBA, &gpio->gpgcon);
+	writel(0x0000FFFF, &gpio->gpgup);
+	writel(0x002AFAAA, &gpio->gphcon);
+	writel(0x000007FF, &gpio->gphup);
+
+	return 0;
+}
 
+int board_init(void)
+{
 	/* arch number of SMDK2410-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
 
@@ -116,11 +124,10 @@ int board_init (void)
 	return 0;
 }
 
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
 	return 0;
 }
 
@@ -134,3 +141,15 @@ int board_eth_init(bd_t *bis)
 	return rc;
 }
 #endif
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29LV800BB flash.
+ */
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	info->portwidth = FLASH_CFI_16BIT;
+	info->chipwidth = FLASH_CFI_BY16;
+	info->interface = FLASH_CFI_X16;
+	return 1;
+}
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index d3189f6..1ad68b9 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -24,7 +24,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/smc.h>
+#include <asm/arch/sromc.h>
 #include <asm/arch/gpio.h>
 #include <netdev.h>
 
@@ -50,7 +50,7 @@ static void smc9115_pre_init(void)
 			| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
 
 	/* Select and configure the SROMC bank */
-	s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
 }
 
 int board_init(void)
diff --git a/board/efikamx/config.mk b/board/samsung/smdkv310/Makefile
index 6e90671..8e9b703 100644
--- a/board/efikamx/config.mk
+++ b/board/samsung/smdkv310/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+# Copyright (C) 2011 Samsung Electronics
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -20,6 +20,27 @@
 # MA 02111-1307 USA
 #
 
-CONFIG_SYS_TEXT_BASE = 0x97800000
-IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
-ALL += $(obj)u-boot.imx
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= mem_setup.o
+SOBJS	+= lowlevel_init.o
+COBJS	+= smdkv310.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
new file mode 100644
index 0000000..04f6579
--- /dev/null
+++ b/board/samsung/smdkv310/lowlevel_init.S
@@ -0,0 +1,470 @@
+/*
+ * Lowlevel setup for SMDKV310 board based on S5PC210
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+#define MEM_DLLl_ON
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	push	{lr}
+
+	/* r5 has always zero */
+	mov	r5, #0
+	ldr	r7, =S5PC210_GPIO_PART1_BASE
+	ldr	r6, =S5PC210_GPIO_PART2_BASE
+
+	/* check reset status  */
+	ldr     r0, =(S5PC210_POWER_BASE + 0x81C)	@ INFORM7
+        ldr     r1, [r0]
+
+	/* AFTR wakeup reset */
+	ldr	r2, =S5P_CHECK_DIDLE
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* Sleep wakeup reset */
+	ldr	r2, =S5P_CHECK_SLEEP
+	cmp	r1, r2
+	beq	wakeup_reset
+
+	/*
+	 * If U-boot is already running in ram, no need to relocate U-Boot.
+	 * Memory controller must be configured before relocating U-Boot
+	 * in ram.
+	 */
+	ldr	r0, =0x00ffffff		/* r0 <- Mask Bits*/
+	bic	r1, pc, r0		/* pc <- current addr of code */
+					/* r1 <- unmasked bits of pc */
+
+	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
+	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
+	cmp     r1, r2                  /* compare r1, r2 */
+	beq     1f			/* r0 == r1 then skip sdram init */
+
+	/* init system clock */
+	bl system_clock_init
+
+	/* Memory initialize */
+	bl mem_ctrl_asm_init
+
+1:
+	/* for UART */
+	bl uart_asm_init
+	bl tzpc_init
+	pop	{pc}
+
+wakeup_reset:
+	bl system_clock_init
+	bl mem_ctrl_asm_init
+	bl tzpc_init
+
+exit_wakeup:
+	/* Load return address and jump to kernel */
+	ldr     r0, =(S5PC210_POWER_BASE + 0x800)	@ INFORM0
+
+	/* r1 = physical address of s5pc210_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel*/
+	mov	pc, r1
+	nop
+	nop
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	push	{lr}
+	ldr	r0, =S5PC210_CLOCK_BASE
+
+	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
+	ldr	r1, =0x0101
+	ldr	r2, =0x14200			@CLK_SRC_CPU
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+2:	subs	r1, r1, #1
+	bne	2b
+
+	ldr	r1, =0x00
+	ldr	r2, =0x0C210			@CLK_SRC_TOP0
+	str	r1, [r0, r2]
+
+	ldr	r1, =0x00
+	ldr	r2, =0x0C214			@CLK_SRC_TOP1_OFFSET
+	str	r1, [r0, r2]
+
+	/* DMC */
+	ldr	r1, =0x00
+	ldr	r2, =0x10200			@CLK_SRC_DMC_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_LEFTBUS */
+	ldr	r1, =0x00
+	ldr	r2, =0x04200			@CLK_SRC_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_RIGHTBUS */
+	ldr	r1, =0x00
+	ldr	r2, =0x08200			@CLK_SRC_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+	ldr	r1, =0x066666
+	ldr	r2, =0x0C240			@ CLK_SRC_FSYS
+	str	r1, [r0, r2]
+
+	/* UART[0:4], PWM: SCLKMPLL(6) */
+	ldr	r1, =0x06666666
+	ldr	r2, =0x0C250			@CLK_SRC_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+3:	subs	r1, r1, #1
+	bne	3b
+
+	/*
+	 * CLK_DIV_CPU0:
+	 *
+	 * PCLK_DBG_RATIO[20]	0x1
+	 * ATB_RATIO[16]	0x3
+	 * PERIPH_RATIO[12]	0x3
+	 * COREM1_RATIO[8]	0x7
+	 * COREM0_RATIO[4]	0x3
+	 */
+	ldr	r1, =0x0133730
+	ldr	r2, =0x14500			@CLK_DIV_CPU0_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_CPU1: COPY_RATIO [0]	0x3 */
+	ldr	r1, =0x03
+	ldr	r2, =0x14504			@CLK_DIV_CPU1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_DMC0:
+	 *
+	 * CORE_TIMERS_RATIO[28]	0x1
+	 * COPY2_RATIO[24]	0x3
+	 * DMCP_RATIO[20]	0x1
+	 * DMCD_RATIO[16]	0x1
+	 * DMC_RATIO[12]	0x1
+	 * DPHY_RATIO[8]	0x1
+	 * ACP_PCLK_RATIO[4]	0x1
+	 * ACP_RATIO[0]		0x3
+	 */
+	ldr	r1, =0x13111113
+	ldr	r2, =0x010500			@CLK_DIV_DMC0_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_DMC1:
+	 *
+	 * DPM_RATIO[24]	0x1
+	 * DVSEM_RATIO[16]	0x1
+	 * PWI_RATIO[8]		0x1
+	 */
+	ldr	r1, =0x01010100
+	ldr	r2, =0x010504			@CLK_DIV_DMC1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_LEFRBUS:
+	 *
+	 * GPL_RATIO[4]		0x1
+	 * GDL_RATIO[0]		0x3
+	 */
+	ldr	r1, =0x013
+	ldr	r2, =0x04500			@CLK_DIV_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_RIGHTBUS:
+	 *
+	 * GPR_RATIO[4]		0x1
+	 * GDR_RATIO[0]		0x3
+	 */
+	ldr	r1, =0x013
+	ldr	r2, =0x08500			@CLK_DIV_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_TOP:
+	 *
+	 * ONENAND_RATIO[16]	0x0
+	 * ACLK_133_RATIO[12]	0x5
+	 * ACLK_160_RATIO[8]	0x4
+	 * ACLK_100_RATIO[4]	0x7
+	 * ACLK_200_RATIO[0]	0x3
+	 */
+	ldr	r1, =0x05473
+	ldr	r2, =0x0C510			@CLK_DIV_TOP_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC[0:1] */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C544			@ CLK_DIV_FSYS1
+	str	r1, [r0, r2]
+
+	/* MMC[2:3] */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C548			@ CLK_DIV_FSYS2
+	str	r1, [r0, r2]
+
+	/* MMC4 */
+	ldr	r1, =0x000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C54C			@ CLK_DIV_FSYS3
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+4:	subs	r1, r1, #1
+	bne	4b
+
+	/*
+	 * CLK_DIV_PERIL0:
+	 *
+	 * UART5_RATIO[20]	8
+	 * UART4_RATIO[16]	8
+	 * UART3_RATIO[12]	8
+	 * UART2_RATIO[8]	8
+	 * UART1_RATIO[4]	8
+	 * UART0_RATIO[0]	8
+	 */
+	ldr	r1, =0x774777
+	ldr	r2, =0x0C550			@CLK_DIV_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* SLIMBUS: ???, PWM */
+	ldr	r1, =0x8
+	ldr	r2, =0x0C55C			@ CLK_DIV_PERIL3
+	str	r1, [r0, r2]
+
+	/* Set PLL locktime */
+	ldr	r1, =0x01C20
+	ldr	r2, =0x014000			@APLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x014008			@MPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x0C010			@EPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x0C020			@VPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * APLL_CON1:
+	 *
+	 * APLL_AFC_ENB[31]	0x1
+	 * APLL_AFC[0]		0xC
+	 */
+	ldr	r1, =0x8000000C
+	ldr	r2, =0x014104			@APLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * APLL_CON0:
+	 *
+	 * APLL_MDIV[16]	0xFA
+	 * APLL_PDIV[8]		0x6
+	 * APLL_SDIV[0]		0x1
+	 */
+	ldr	r1, =0x80FA0601
+	ldr	r2, =0x014100			@APLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * MPLL_CON1:
+	 *
+	 * MPLL_AFC_ENB[31]	0x1
+	 * MPLL_AFC[0]		0x1C
+	 */
+	ldr	r1, =0x0000001C
+	ldr	r2, =0x01410C			@MPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * MPLL_CON0:
+	 *
+	 * MPLL_MDIV[16]	0xC8
+	 * MPLL_PDIV[8]		0x6
+	 * MPLL_SDIV[0]		0x1
+	 */
+	ldr	r1, =0x80C80601
+	ldr	r2, =0x014108			@MPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* EPLL */
+	ldr	r1, =0x0
+	ldr	r2, =0x0C114			@EPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * EPLL_CON0:
+	 *
+	 * EPLL_MDIV[16]	0x30
+	 * EPLL_PDIV[8]		0x3
+	 * EPLL_SDIV[0]		0x2
+	 */
+	ldr	r1, =0x80300302
+	ldr	r2, =0x0C110			@EPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * VPLL_CON1:
+	 *
+	 * VPLL_MRR[24]		0x11
+	 * VPLL_MFR[16]		0x0
+	 * VPLL_K[0]		0x400
+	 */
+	ldr	r1, =0x11000400
+	ldr	r2, =0x0C124			@VPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * VPLL_CON0:
+	 *
+	 * VPLL_MDIV[16]	0x35
+	 * VPLL_PDIV[8]		0x3
+	 * VPLL_SDIV[0]		0x2
+	 */
+	ldr	r1, =0x80350302
+	ldr	r2, =0x0C120			@VPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+3:	subs	r1, r1, #1
+	bne	3b
+
+	pop	{pc}
+/*
+ * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
+ * void uart_asm_init(void)
+ */
+	.globl uart_asm_init
+uart_asm_init:
+
+	/* setup UART0-UART3 GPIOs (part1) */
+	mov	r0, r7
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x00]			@ S5PC210_GPIO_A0_OFFSET
+	ldr	r1, =0x00222222
+	str	r1, [r0, #0x20]			@ S5PC210_GPIO_A1_OFFSET
+
+	ldr r0, =S5PC210_UART_BASE
+	add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+
+	ldr r1, =0x3C5
+	str	r1, [r0, #0x4]
+	ldr r1, =0x111
+	str	r1, [r0, #0x8]
+	ldr r1, =0x3
+	str	r1, [r0, #0x0]
+	ldr r1, =0x35
+	str	r1, [r0, #0x28]
+	ldr r1, =0x4
+	str	r1, [r0, #0x2c]
+
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+/* Setting TZPC[TrustZone Protection Controller] */
+tzpc_init:
+	ldr	r0, =0x10110000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10120000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10130000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10140000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10150000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10160000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	mov	pc, lr
diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S
new file mode 100644
index 0000000..73aebe3
--- /dev/null
+++ b/board/samsung/smdkv310/mem_setup.S
@@ -0,0 +1,365 @@
+/*
+ * Memory setup for SMDKV310 board based on S5PC210
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#define SET_MIU
+
+#define MEM_DLL
+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_200_200
+#define DRAM_CLK_200
+#endif
+#ifdef CONFIG_CLK_1000_330_165
+#define DRAM_CLK_330
+#endif
+#ifdef CONFIG_CLK_1000_400_200
+#define DRAM_CLK_400
+#endif
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+
+	/*
+	* Async bridge configuration at CPU_core:
+	* 1: half_sync
+	* 0: full_sync
+	*/
+	ldr r0, =0x10010350
+	mov r1, #1
+	str r1, [r0]
+
+#ifdef SET_MIU
+	ldr	r0, =S5PC210_MIU_BASE	@0x10600000
+#ifdef CONFIG_MIU_1BIT_INTERLEAVED
+	ldr	r1, =0x0000000c
+	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
+	ldr	r1, =0xbfffffff
+	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#ifdef CONFIG_MIU_2BIT_INTERLEAVED
+	ldr	r1, =0x2000150c
+	str	r1, [r0, #0x400]	@MIU_INTLV_CONFIG
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x808]	@MIU_INTLV_START_ADDR
+	ldr	r1, =0xbfffffff
+	str	r1, [r0, #0x810]	@MIU_INTLV_END_ADDR
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#ifdef CONFIG_MIU_LINEAR
+	ldr	r1, =0x40000000
+	str	r1, [r0, #0x818]	@MIU_SINGLE_MAPPING0_START_ADDR
+	ldr	r1, =0x7fffffff
+	str	r1, [r0, #0x820]	@MIU_SINGLE_MAPPING0_END_ADDR
+	ldr	r1, =0x80000000
+	str	r1, [r0, #0x828]	@MIU_SINGLE_MAPPING1_START_ADDR
+	ldr	r1, =0xbfffffff
+	str	r1, [r0, #0x830]	@MIU_SINGLE_MAPPING1_END_ADDR]
+	ldr	r1, =0x00000006
+	str	r1, [r0, #0x800]	@MIU_MAPPING_UPDATE
+#endif
+#endif
+	/* DREX0 */
+	ldr	r0, =S5PC210_DMC0_BASE	@0x10400000
+
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00312640
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+
+#ifdef CONFIG_MIU_LINEAR
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x60e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#endif
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x000000BC
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x3545548d
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x45430506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x4439033c
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x56500506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x5444033d
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	ldr	r1, =0x00020000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00030000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00010002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	ldr	r1, =0x00120000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00130000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00110002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00100328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+	/* DREX1 */
+	ldr	r0, =S5PC210_DMC1_BASE	@0x10410000
+
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00312640
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+
+#ifdef CONFIG_MIU_LINEAR
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x60e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#endif
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x000000BC
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x3545548d
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x45430506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x4439033c
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x56500506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x5444033d
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	ldr	r1, =0x00020000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00030000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00010002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	ldr	r1, =0x00120000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00130000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00110002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00100328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+	/* turn on DREX0, DREX1 */
+	ldr	r0, =0x10400000		@APB_DMC_0_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+
+	ldr	r0, =0x10410000		@APB_DMC_1_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+
+	mov	pc, lr
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
new file mode 100644
index 0000000..acf9ee7
--- /dev/null
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sromc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct s5pc210_gpio_part1 *gpio1;
+struct s5pc210_gpio_part2 *gpio2;
+
+static void smc9115_pre_init(void)
+{
+	u32 smc_bw_conf, smc_bc_conf;
+
+	/* gpio configuration GPK0CON */
+	gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+
+	/* Ethernet needs bus width of 16 bits */
+	smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+	smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
+			| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
+			| SROMC_BC_TAH(0x0F)  | SROMC_BC_TACP(0x0F)
+			| SROMC_BC_PMC(0x0F);
+
+	/* Select and configure the SROMC bank */
+	s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
+int board_init(void)
+{
+	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+	smc9115_pre_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_SMDKV310;
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: SMDKV310\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i, err;
+
+	/*
+	 * MMC2 SD card GPIO:
+	 *
+	 * GPK2[0]	SD_2_CLK(2)
+	 * GPK2[1]	SD_2_CMD(2)
+	 * GPK2[2]	SD_2_CDn
+	 * GPK2[3:6]	SD_2_DATA[0:3](2)
+	 */
+	for (i = 0; i < 7; i++) {
+		/* GPK2[0:6] special function 2 */
+		gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+
+		/* GPK2[0:6] drv 4x */
+		gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+
+		/* GPK2[0:1] pull disable */
+		if (i == 0 || i == 1) {
+			gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			continue;
+		}
+
+		/* GPK2[2:6] pull up */
+		gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+	}
+	err = s5p_mmc_init(2, 4);
+	return err;
+}
+#endif
diff --git a/board/ttcontrol/vision2/config.mk b/board/st-ericsson/u8500/Makefile
index 952037e..91c2abf 100644
--- a/board/ttcontrol/vision2/config.mk
+++ b/board/st-ericsson/u8500/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+# Copyright (C) ST-Ericsson SA 2009
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -20,6 +20,31 @@
 # MA 02111-1307 USA
 #
 
-CONFIG_SYS_TEXT_BASE = 0x97800000
-IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg
-ALL += $(obj)u-boot.imx
+include $(TOPDIR)/config.mk
+
+CFLAGS += -D__RELEASE -D__STN_8500
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= u8500_href.o gpio.o prcmu.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/st-ericsson/u8500/gpio.c b/board/st-ericsson/u8500/gpio.c
new file mode 100644
index 0000000..96b2461
--- /dev/null
+++ b/board/st-ericsson/u8500/gpio.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+
+static struct gpio_register *addr_gpio_register[] = {
+	(void *)U8500_GPIO_0_BASE,
+	(void *)U8500_GPIO_1_BASE,
+	(void *)U8500_GPIO_2_BASE,
+	(void *)U8500_GPIO_3_BASE,
+	(void *)U8500_GPIO_4_BASE,
+	(void *)U8500_GPIO_5_BASE,
+	(void *)U8500_GPIO_6_BASE,
+	(void *)U8500_GPIO_7_BASE,
+	(void *)U8500_GPIO_8_BASE,
+};
+
+struct gpio_altfun_data altfun_table[] = {
+	{
+		.altfun = GPIO_ALT_I2C_0,
+		.start = 147,
+		.end = 148,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_I2C_1,
+		.start = 16,
+		.end = 17,
+		.cont = 0,
+		.type = GPIO_ALTF_B,
+	},
+	{
+		.altfun = GPIO_ALT_I2C_2,
+		.start = 10,
+		.end = 11,
+		.cont = 0,
+		.type = GPIO_ALTF_B,
+	},
+	{
+		.altfun = GPIO_ALT_I2C_3,
+		.start = 229,
+		.end = 230,
+		.cont = 0,
+		.type = GPIO_ALTF_C,
+	},
+	{
+		.altfun = GPIO_ALT_UART_0_MODEM,
+		.start = 0,
+		.end = 3,
+		.cont = 1,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_UART_0_MODEM,
+		.start = 33,
+		.end = 36,
+		.cont = 0,
+		.type = GPIO_ALTF_C,
+	},
+	{
+		.altfun = GPIO_ALT_UART_1,
+		.start = 4,
+		.end = 7,
+		.cont = 0,
+		.type =
+			GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_UART_2,
+		.start = 18,
+		.end = 19,
+		.cont = 1,
+		.type = GPIO_ALTF_B,
+	},
+	{
+		.altfun = GPIO_ALT_UART_2,
+		.start = 29,
+		.end = 32,
+		.cont = 0,
+		.type = GPIO_ALTF_C,
+	},
+	{
+		.altfun = GPIO_ALT_MSP_0,
+		.start = 12,
+		.end = 17,
+		.cont = 1,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_MSP_0,
+		.start = 21,
+		.end = 21,
+		.cont = 0,
+		.type = GPIO_ALTF_B,
+	},
+	{
+		.altfun = GPIO_ALT_MSP_1,
+		.start = 33,
+		.end = 36,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_MSP_2,
+		.start = 192,
+		.end = 196,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_LCD_PANEL,
+		.start = 64,
+		.end = 93,
+		.cont = 1,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_LCD_PANEL,
+		.start = 150,
+		.end = 171,
+		.cont = 0,
+		.type = GPIO_ALTF_B,
+	},
+	{
+		.altfun = GPIO_ALT_SD_CARD0,
+		.start = 18,
+		.end = 28,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_MM_CARD0,
+		.start = 18,
+		.end = 32,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_USB_OTG,
+		.start = 256,
+		.end = 267,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_EMMC,
+		.start = 197,
+		.end = 207,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+	{
+		.altfun = GPIO_ALT_POP_EMMC,
+		.start = 128,
+		.end = 138,
+		.cont = 0,
+		.type = GPIO_ALTF_A,
+	},
+};
+
+/*
+ * Static Function declarations
+ */
+enum gpio_error gpio_setpinconfig(int pin_id, struct gpio_config *config)
+{
+	struct gpio_register *p_gpio_register =
+	    addr_gpio_register[GPIO_BLOCK(pin_id)];
+	u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+	enum gpio_error error = GPIO_OK;
+	u32 temp_reg;
+
+	switch (config->mode) {
+	case GPIO_ALTF_A:
+		temp_reg = readl(&p_gpio_register->gpio_afsa);
+		temp_reg |= mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsa);
+		temp_reg = readl(&p_gpio_register->gpio_afsb);
+		temp_reg &= ~mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsb);
+		break;
+	case GPIO_ALTF_B:
+		temp_reg = readl(&p_gpio_register->gpio_afsa);
+		temp_reg &= ~mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsa);
+		temp_reg = readl(&p_gpio_register->gpio_afsb);
+		temp_reg |= mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsb);
+		break;
+	case GPIO_ALTF_C:
+		temp_reg = readl(&p_gpio_register->gpio_afsa);
+		temp_reg |= mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsa);
+		temp_reg = readl(&p_gpio_register->gpio_afsb);
+		temp_reg |= mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsb);
+		break;
+	case GPIO_MODE_SOFTWARE:
+		temp_reg = readl(&p_gpio_register->gpio_afsa);
+		temp_reg &= ~mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsa);
+		temp_reg = readl(&p_gpio_register->gpio_afsb);
+		temp_reg &= ~mask;
+		writel(temp_reg, &p_gpio_register->gpio_afsb);
+
+		switch (config->direction) {
+		case GPIO_DIR_INPUT:
+			writel(mask, &p_gpio_register->gpio_dirc);
+			break;
+		case GPIO_DIR_OUTPUT:
+			writel(mask, &p_gpio_register->gpio_dirs);
+			break;
+		case GPIO_DIR_LEAVE_UNCHANGED:
+			break;
+		default:
+			return GPIO_INVALID_PARAMETER;
+		}
+
+		break;
+	case GPIO_MODE_LEAVE_UNCHANGED:
+		break;
+	default:
+		return GPIO_INVALID_PARAMETER;
+	}
+	return error;
+}
+
+enum gpio_error gpio_resetgpiopin(int pin_id, char *dev_name)
+{
+	struct gpio_register *p_gpio_register =
+	    addr_gpio_register[GPIO_BLOCK(pin_id)];
+	u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+	enum gpio_error error = GPIO_OK;
+	u32 temp_reg;
+
+	temp_reg = readl(&p_gpio_register->gpio_afsa);
+	temp_reg &= ~mask;
+	writel(temp_reg, &p_gpio_register->gpio_afsa);
+	temp_reg = readl(&p_gpio_register->gpio_afsb);
+	temp_reg &= ~mask;
+	writel(temp_reg, &p_gpio_register->gpio_afsb);
+	writel(mask, &p_gpio_register->gpio_dirc);
+
+	return error;
+}
+
+struct gpio_config altfun_pinconfig;
+enum gpio_error gpio_altfunction(enum gpio_alt_function alt_func,
+			    int which_altfunc, char *dev_name)
+{
+	int i, j, start, end;
+	enum gpio_error error = -1;
+
+	for (i = 0; i < ARRAY_SIZE(altfun_table); i++) {
+		if (altfun_table[i].altfun != alt_func)
+			continue;
+
+		start = altfun_table[i].start;
+		end = altfun_table[i].end;
+		for (j = start; j <= end; j++) {
+			if (which_altfunc == GPIO_ALTF_FIND)
+				altfun_pinconfig.mode = altfun_table[i].type;
+			else
+				altfun_pinconfig.mode = which_altfunc;
+			altfun_pinconfig.direction = GPIO_DIR_OUTPUT;
+			altfun_pinconfig.dev_name = dev_name;
+
+			if (which_altfunc != GPIO_ALTF_DISABLE)
+				error = gpio_setpinconfig(j, &altfun_pinconfig);
+			else
+				error = gpio_resetgpiopin(j, dev_name);
+			if (!error)
+				continue;
+			printf("GPIO %d configuration failure (nmdk_error:%d)",
+				j, error);
+			error = GPIO_INVALID_PARAMETER;
+			return error;
+		}
+
+		if (!altfun_table[i].cont)
+			break;
+	}
+	return error;
+}
+
+int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name)
+{
+	struct gpio_register *p_gpio_register =
+	    addr_gpio_register[GPIO_BLOCK(pin_id)];
+	u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+
+	switch (value) {
+	case GPIO_DATA_HIGH:
+		writel(mask, &p_gpio_register->gpio_dats);
+		break;
+	case GPIO_DATA_LOW:
+		writel(mask, &p_gpio_register->gpio_datc);
+		break;
+	default:
+		printf("Invalid value passed in %s", __FUNCTION__);
+		return GPIO_INVALID_PARAMETER;
+	}
+	return GPIO_OK;
+}
+
+int gpio_readpin(int pin_id, enum gpio_data *rv)
+{
+	struct gpio_register *p_gpio_register =
+	    addr_gpio_register[GPIO_BLOCK(pin_id)];
+	u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+
+	if ((readl(&p_gpio_register->gpio_dat) & mask) != 0)
+		*rv = GPIO_DATA_HIGH;
+	else
+		*rv = GPIO_DATA_LOW;
+	return GPIO_OK;
+}
+
+int gpio_altfuncenable(enum gpio_alt_function altfunc, char *dev_name)
+{
+	return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name);
+}
+
+int gpio_altfuncdisable(enum gpio_alt_function altfunc, char *dev_name)
+{
+	return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name);
+}
diff --git a/board/st-ericsson/u8500/prcmu-fw.h b/board/st-ericsson/u8500/prcmu-fw.h
new file mode 100644
index 0000000..0836983
--- /dev/null
+++ b/board/st-ericsson/u8500/prcmu-fw.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson SA
+ *
+ * Copied from the Linux version:
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __MACH_PRCMU_FW_V1_H
+#define __MACH_PRCMU_FW_V1_H
+
+#define AP_EXECUTE	2
+#define I2CREAD		1
+#define I2C_WR_OK	1
+#define I2C_RD_OK	2
+#define I2CWRITE	0
+
+#define _PRCMU_TCDM_BASE    U8500_PRCMU_TCDM_BASE
+#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC)      /* 4 BYTES */
+
+#define PRCM_REQ_MB5        (_PRCMU_TCDM_BASE + 0xE44)    /* 4 bytes  */
+#define PRCM_ACK_MB5        (_PRCMU_TCDM_BASE + 0xDF4)    /* 4 bytes */
+
+/* Mailbox 5 Requests */
+#define PRCM_REQ_MB5_I2COPTYPE_REG	(PRCM_REQ_MB5 + 0x0)
+#define PRCM_REQ_MB5_BIT_FIELDS		(PRCM_REQ_MB5 + 0x1)
+#define PRCM_REQ_MB5_I2CSLAVE		(PRCM_REQ_MB5 + 0x2)
+#define PRCM_REQ_MB5_I2CVAL		(PRCM_REQ_MB5 + 0x3)
+
+/* Mailbox 5 ACKs */
+#define PRCM_ACK_MB5_STATUS	(PRCM_ACK_MB5 + 0x1)
+#define PRCM_ACK_MB5_SLAVE	(PRCM_ACK_MB5 + 0x2)
+#define PRCM_ACK_MB5_VAL	(PRCM_ACK_MB5 + 0x3)
+
+#define LOW_POWER_WAKEUP	1
+#define EXE_WAKEUP		0
+
+#define REQ_MB5			5
+
+extern int prcmu_i2c_read(u8 reg, u16 slave);
+extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+
+#endif /* __MACH_PRCMU_FW_V1_H */
diff --git a/board/st-ericsson/u8500/prcmu.c b/board/st-ericsson/u8500/prcmu.c
new file mode 100644
index 0000000..6f9302f
--- /dev/null
+++ b/board/st-ericsson/u8500/prcmu.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson SA
+ *
+ * Adapted from the Linux version:
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+/*
+ * NOTE: This currently does not support the I2C workaround access method.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#include "prcmu-fw.h"
+
+/* CPU mailbox registers */
+#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc)
+#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100)
+#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104)
+
+static int prcmu_is_ready(void)
+{
+	int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
+	if (!ready)
+		printf("PRCMU firmware not ready\n");
+	return ready;
+}
+
+static int _wait_for_req_complete(int num)
+{
+	int timeout = 1000;
+
+	/* checking any already on-going transaction */
+	while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--)
+		;
+
+	timeout = 1000;
+
+	/* Set an interrupt to XP70 */
+	writel(1 << num, PRCM_MBOX_CPU_SET);
+
+	while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--)
+		;
+
+	if (!timeout) {
+		printf("PRCMU operation timed out\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
+ * @reg: - db8500 register bank to be accessed
+ * @slave:  - db8500 register to be accessed
+ * Returns: ACK_MB5  value containing the status
+ */
+int prcmu_i2c_read(u8 reg, u16 slave)
+{
+	uint8_t i2c_status;
+	uint8_t i2c_val;
+
+	if (!prcmu_is_ready())
+		return -1;
+
+	debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
+			reg, slave);
+
+	/* prepare the data for mailbox 5 */
+	writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG);
+	writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
+	writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
+	writeb(0, PRCM_REQ_MB5_I2CVAL);
+
+	_wait_for_req_complete(REQ_MB5);
+
+	/* retrieve values */
+	debug("ack-mb5:transfer status = %x\n",
+			readb(PRCM_ACK_MB5_STATUS));
+	debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
+	debug("ack-mb5:slave_add = %x\n",
+			readb(PRCM_ACK_MB5_SLAVE));
+	debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
+
+	i2c_status = readb(PRCM_ACK_MB5_STATUS);
+	i2c_val = readb(PRCM_ACK_MB5_VAL);
+
+	if (i2c_status == I2C_RD_OK)
+		return i2c_val;
+	else {
+
+		printf("prcmu_i2c_read:read return status= %d\n",
+				i2c_status);
+		return -1;
+	}
+
+}
+
+/**
+ * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
+ * @reg: - db8500 register bank to be accessed
+ * @slave:  - db800 register to be written to
+ * @reg_data: - the data to write
+ * Returns: ACK_MB5 value containing the status
+ */
+int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
+{
+	uint8_t i2c_status;
+
+	if (!prcmu_is_ready())
+		return -1;
+
+	debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
+			reg, slave);
+
+	/* prepare the data for mailbox 5 */
+	writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG);
+	writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
+	writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
+	writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
+
+	debug("\ncpu_is_u8500v11\n");
+	_wait_for_req_complete(REQ_MB5);
+
+	/* retrieve values */
+	debug("ack-mb5:transfer status = %x\n",
+			readb(PRCM_ACK_MB5_STATUS));
+	debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
+	debug("ack-mb5:slave_add = %x\n",
+			readb(PRCM_ACK_MB5_SLAVE));
+	debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
+
+	i2c_status = readb(PRCM_ACK_MB5_STATUS);
+	debug("\ni2c_status = %x\n", i2c_status);
+	if (i2c_status == I2C_WR_OK)
+		return 0;
+	else {
+		printf("ape-i2c: i2c_status : 0x%x\n", i2c_status);
+		return -1;
+	}
+}
diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c
new file mode 100644
index 0000000..525633e
--- /dev/null
+++ b/board/st-ericsson/u8500/u8500_href.c
@@ -0,0 +1,546 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <i2c.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_MMC
+#include "../../../drivers/mmc/arm_pl180_mmci.h"
+#endif
+
+#define NOMADIK_PER4_BASE	(0x80150000)
+#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
+#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
+
+/* Power, Reset, Clock Management Unit */
+/*
+ * SVA: Smart Video Accelerator
+ * SIA: Smart Imaging Accelerator
+ * SGA: Smart Graphic accelerator
+ * B2R2: Graphic blitter
+ */
+#define PRCMU_BASE	CFG_PRCMU_BASE	/* 0x80157000 for U8500 */
+#define PRCM_ARMCLKFIX_MGT_REG		(PRCMU_BASE + 0x000)
+#define PRCM_ACLK_MGT_REG		(PRCMU_BASE + 0x004)
+#define PRCM_SVAMMDSPCLK_MGT_REG	(PRCMU_BASE + 0x008)
+#define PRCM_SIAMMDSPCLK_MGT_REG	(PRCMU_BASE + 0x00C)
+#define PRCM_SAAMMDSPCLK_MGT_REG	(PRCMU_BASE + 0x010)
+#define PRCM_SGACLK_MGT_REG		(PRCMU_BASE + 0x014)
+#define PRCM_UARTCLK_MGT_REG		(PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG		(PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG		(PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG		(PRCMU_BASE + 0x024)
+#define PRCM_SLIMCLK_MGT_REG		(PRCMU_BASE + 0x028)
+#define PRCM_PER1CLK_MGT_REG		(PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG		(PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG		(PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG		(PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG		(PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG		(PRCMU_BASE + 0x040)
+#define PRCM_DMACLK_MGT_REG		(PRCMU_BASE + 0x074)
+#define PRCM_B2R2CLK_MGT_REG		(PRCMU_BASE + 0x078)
+
+#define PRCM_PLLSOC0_FREQ_REG		(PRCMU_BASE + 0x080)
+#define PRCM_PLLSOC1_FREQ_REG		(PRCMU_BASE + 0x084)
+#define PRCM_PLLARM_FREQ_REG		(PRCMU_BASE + 0x088)
+#define PRCM_PLLDDR_FREQ_REG		(PRCMU_BASE + 0x08C)
+#define PRCM_ARM_CHGCLKREQ_REG		(PRCMU_BASE + 0x114)
+
+#define PRCM_TCR			(PRCMU_BASE + 0x1C8)
+
+/*
+ * Memory controller register
+ */
+#define DMC_BASE_ADDR			0x80156000
+#define DMC_CTL_97			(DMC_BASE_ADDR + 0x184)
+
+int board_id;	/* set in board_late_init() */
+
+/* PLLs for clock management registers */
+enum {
+	GATED = 0,
+	PLLSOC0,	/* pllsw = 001, ffs() = 1 */
+	PLLSOC1,	/* pllsw = 010, ffs() = 2 */
+	PLLDDR,		/* pllsw = 100, ffs() = 3 */
+	PLLARM,
+};
+
+static struct pll_freq_regs {
+	int idx;	/* index fror pll_name and pll_khz arrays */
+	uint32_t addr;
+} pll_freq_regs[] = {
+	{PLLSOC0, PRCM_PLLSOC0_FREQ_REG},
+	{PLLSOC1, PRCM_PLLSOC1_FREQ_REG},
+	{PLLDDR, PRCM_PLLDDR_FREQ_REG},
+	{PLLARM, PRCM_PLLARM_FREQ_REG},
+	{0, 0},
+};
+
+static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"};
+static uint32_t pll_khz[5];	/* use ffs(pllsw(reg)) as index for 0..3 */
+
+static struct clk_mgt_regs {
+	uint32_t addr;
+	uint32_t val;
+	const char *descr;
+} clk_mgt_regs[] = {
+	/* register content taken from bootrom settings */
+	{PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
+	{PRCM_ACLK_MGT_REG, 0x0125, "ACLK"},	/* ena, SOC0/5, 160 MHz */
+	{PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
+	{PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
+	{PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
+	{PRCM_SGACLK_MGT_REG, 0x0024, "SGA"},	/* dis, SOC0/4, 200 MHz */
+	{PRCM_UARTCLK_MGT_REG, 0x0300, "UART"},	/* ena, GATED, CLK38 */
+	{PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"},	/* dis, GATED, CLK38 */
+	{PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"},	/* ena, SOC0/16, 50 MHz */
+	{PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
+	{PRCM_PER1CLK_MGT_REG, 0x126, "PER1"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER2CLK_MGT_REG, 0x126, "PER2"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER3CLK_MGT_REG, 0x126, "PER3"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER5CLK_MGT_REG, 0x126, "PER5"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER6CLK_MGT_REG, 0x126, "PER6"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER7CLK_MGT_REG, 0x128, "PER7"},	/* ena, SOC0/8, 100 MHz */
+	{PRCM_DMACLK_MGT_REG, 0x125, "DMA"},	/* ena, SOC0/5, 160 MHz */
+	{PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"},	/* dis, SOC0/5, 160 MHz */
+	{0, 0, NULL},
+};
+
+static void init_regs(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static unsigned int read_asicid(void)
+{
+	unsigned int *address = (void *)U8500_BOOTROM_BASE
+				+ U8500_BOOTROM_ASIC_ID_OFFSET;
+	return readl(address);
+}
+
+int cpu_is_u8500v11(void)
+{
+	return read_asicid() == 0x008500A1;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f(void)
+{
+	init_regs();
+	return 0;
+}
+
+int board_init(void)
+{
+	uint32_t unused_cols_rows;
+	unsigned int nrows;
+	unsigned int ncols;
+
+	gd->bd->bi_arch_number = 0x1A4;
+	gd->bd->bi_boot_params = 0x00000100;
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+
+	/*
+	 * Assumption: 2 CS active, both CS have same layout.
+	 *             15 rows max, 11 cols max (controller spec).
+	 *             memory chip has 8 banks, I/O width 32 bit.
+	 * The correct way would be to read MR#8: I/O width and density,
+	 * but this requires locking against the PRCMU firmware.
+	 * Simplified approach:
+	 * Read number of unused rows and columns from mem controller.
+	 * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
+	 */
+	unused_cols_rows = readl(DMC_CTL_97);
+	nrows = 15 - (unused_cols_rows & 0x07);
+	ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
+	gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4;
+
+	icache_enable();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE_1;
+
+	return 0;
+}
+
+unsigned int addr_vall_arr[] = {
+	0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */
+	0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */
+	0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
+	0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
+	0x80157020, 0x00000150, /* I2C 48MHz clock */
+	0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
+	0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
+	0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
+	0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
+	0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
+	0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
+	0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
+	0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
+	0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
+	0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
+	0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
+	0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
+	0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
+				   PRCM_APE_RESETN_SET_REG */
+	0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
+	0xA03FF000, 0x00000003, /* USB */
+	0xA03FF008, 0x00000001, /* USB */
+	0xA03FE00C, 0x00000000, /* USB */
+	0xA03FE020, 0x00000FFF, /* USB */
+	0xA03FE024, 0x00000000	/* USB */
+};
+
+#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_MMC
+
+#define LDO_VAUX3_MASK		0x3
+#define LDO_VAUX3_ENABLE	0x1
+#define VAUX3_VOLTAGE_2_9V	0xd
+
+#define AB8500_REGU_CTRL2	0x4
+#define AB8500_REGU_VRF1VAUX3_REGU_REG	0x040A
+#define AB8500_REGU_VRF1VAUX3_SEL_REG	0x0421
+
+static int hrefplus_mmc_power_init(void)
+{
+	int ret;
+	int val;
+
+	if (!cpu_is_u8500v11())
+		return 0;
+
+	/*
+	 * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
+	 * card to work.  This is done by enabling the regulators in the AB8500
+	 * via PRCMU I2C transactions.
+	 *
+	 * This code is derived from the handling of AB8500_LDO_VAUX3 in
+	 * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
+	 *
+	 * Turn off and delay is required to have it work across soft reboots.
+	 */
+
+	ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG);
+	if (ret < 0)
+		goto out;
+
+	val = ret;
+
+	/* Turn off */
+	ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG,
+				val & ~LDO_VAUX3_MASK);
+	if (ret < 0)
+		goto out;
+
+	udelay(10 * 1000);
+
+	/* Set the voltage to 2.9V */
+	ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
+				AB8500_REGU_VRF1VAUX3_SEL_REG,
+				VAUX3_VOLTAGE_2_9V);
+	if (ret < 0)
+		goto out;
+
+	val = val & ~LDO_VAUX3_MASK;
+	val = val | LDO_VAUX3_ENABLE;
+
+	/* Turn on the supply */
+	ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
+				AB8500_REGU_VRF1VAUX3_REGU_REG, val);
+
+out:
+	return ret;
+}
+#endif
+/*
+ * called after all initialisation were done, but before the generic
+ * mmc_initialize().
+ */
+int board_late_init(void)
+{
+	uchar byte;
+
+	/*
+	 * Determine and set board_id environment variable
+	 * 0: mop500, 1: href500
+	 * Above boards have different GPIO expander chips which we can
+	 * distinguish by the chip id.
+	 *
+	 * The board_id environment variable is needed for the Linux bootargs.
+	 */
+	(void) i2c_set_bus_num(0);
+	(void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
+	if (byte == 0x01) {
+		board_id = 0;
+		setenv("board_id", "0");
+	} else {
+		board_id = 1;
+		setenv("board_id", "1");
+	}
+#ifdef CONFIG_MMC
+	hrefplus_mmc_power_init();
+
+	/*
+	 * config extended GPIO pins for level shifter and
+	 * SDMMC_ENABLE
+	 */
+	if (board_id == 0) {
+		/* MOP500 */
+		byte = 0x0c;
+		(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1);
+		(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1);
+	} else {
+		/* HREF */
+		/* set the direction of GPIO KPY9 and KPY10 */
+		byte = 0x06;
+		(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1);
+		/* must be a multibyte access */
+		(void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1,
+						(uchar []) {0x06, 0x06}, 2);
+	}
+#endif /* CONFIG_MMC */
+	/*
+	 * Create a memargs variable which points uses either the memargs256 or
+	 * memargs512 environment variable, depending on the memory size.
+	 * memargs is used to build the bootargs, memargs256 and memargs512 are
+	 * stored in the environment.
+	 */
+	if (gd->bd->bi_dram[0].size == 0x10000000) {
+		setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}");
+		setenv("mem", "256M");
+	} else {
+		setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}");
+		setenv("mem", "512M");
+	}
+
+	return 0;
+}
+#endif /* BOARD_LATE_INIT */
+
+static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
+{
+	writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats);
+	writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis);
+}
+
+static void init_regs(void)
+{
+	/* FIXME Remove magic register array settings for ED also */
+	struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
+
+	/* Enable timers */
+	writel(1 << 17, &prcmu->tcr);
+
+	u8500_prcmu_enable(&prcmu->per1clk_mgt);
+	u8500_prcmu_enable(&prcmu->per2clk_mgt);
+	u8500_prcmu_enable(&prcmu->per3clk_mgt);
+	u8500_prcmu_enable(&prcmu->per5clk_mgt);
+	u8500_prcmu_enable(&prcmu->per6clk_mgt);
+	u8500_prcmu_enable(&prcmu->per7clk_mgt);
+
+	u8500_prcmu_enable(&prcmu->uartclk_mgt);
+	u8500_prcmu_enable(&prcmu->i2cclk_mgt);
+
+	u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
+
+	u8500_clock_enable(1, 9, -1);	/* GPIO0 */
+
+	u8500_clock_enable(2, 11, -1);	/* GPIO1 */
+
+	u8500_clock_enable(3, 8, -1);	/* GPIO2 */
+	u8500_clock_enable(5, 1, -1);	/* GPIO3 */
+
+	u8500_clock_enable(3, 6, 6);	/* UART2 */
+
+	gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0");
+	u8500_clock_enable(3, 3, 3);	/* I2C0 */
+
+	early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000);
+	gpio_altfuncenable(GPIO_ALT_UART_2, "UART2");
+
+	early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0);
+	gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC");
+
+	early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0);
+	gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD");
+
+	u8500_clock_enable(1, 5, 5);	/* SDI0 */
+	u8500_clock_enable(2, 4, 2);	/* SDI4 */
+
+	u8500_clock_enable(6, 7, -1);	/* MTU0 */
+	u8500_clock_enable(3, 4, 4);	/* SDI2 */
+
+	early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff);
+	gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC");
+
+	/*
+	 * Enabling clocks for all devices which are AMBA devices in the
+	 * kernel.  Otherwise they will not get probe()'d because the
+	 * peripheral ID register will not be powered.
+	 */
+
+	/* XXX: some of these differ between ED/V1 */
+
+	u8500_clock_enable(1, 1, 1);	/* UART1 */
+	u8500_clock_enable(1, 0, 0);	/* UART0 */
+
+	u8500_clock_enable(3, 2, 2);	/* SSP1 */
+	u8500_clock_enable(3, 1, 1);	/* SSP0 */
+
+	u8500_clock_enable(2, 8, -1);	/* SPI0 */
+	u8500_clock_enable(2, 5, 3);	/* MSP2 */
+}
+
+#ifdef CONFIG_MMC
+static int u8500_mmci_board_init(void)
+{
+	enum gpio_error error;
+	struct gpio_register *gpio_base_address;
+
+	gpio_base_address = (void *)(U8500_GPIO_0_BASE);
+	gpio_base_address->gpio_dats |= 0xFFC0000;
+	gpio_base_address->gpio_pdis &= ~0xFFC0000;
+
+	/* save the GPIO0 AFSELA register */
+	error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC");
+	if (error != GPIO_OK) {
+		printf("u8500_mmci_board_init() gpio_altfuncenable failed\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+int board_mmc_init(bd_t *bd)
+{
+	if (u8500_mmci_board_init())
+		return -ENODEV;
+
+	if (arm_pl180_mmci_init())
+		return -ENODEV;
+	return 0;
+}
+#endif
+
+
+/*
+ * get_pll_freq_khz - return PLL frequency in kHz
+ */
+static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
+{
+	uint32_t idf, ldf, odf, seldiv, phi;
+
+	/*
+	 * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
+	 * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
+	 * where:
+	 * IDF=R(2:0) (when R=000, IDF=1d)
+	 * LDF = 2*D(7:0) (D must be greater than or equal to 6)
+	 * ODF = N(5:0) (when N=000000, 0DF=1d)
+	 */
+
+	idf = (freq_reg & 0x70000) >> 16;
+	ldf = (freq_reg & 0xff) * 2;
+	odf = (freq_reg & 0x3f00) >> 8;
+	seldiv = (freq_reg & 0x01000000) >> 24;
+	phi = (inclk_khz * ldf) / (2 * odf * idf);
+	if (seldiv)
+		phi = phi/2;
+
+	return phi;
+}
+
+int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uint32_t inclk_khz;
+	uint32_t reg, phi;
+	uint32_t clk_khz;
+	unsigned int clk_sel;
+	struct clk_mgt_regs *clks = clk_mgt_regs;
+	struct pll_freq_regs *plls = pll_freq_regs;
+
+	/*
+	 * Go through list of PLLs.
+	 * Initialise pll out frequency array (pll_khz) and print frequency.
+	 */
+	inclk_khz = 38400;	/* 38.4 MHz */
+	while (plls->addr) {
+		reg = readl(plls->addr);
+		phi = get_pll_freq_khz(inclk_khz, reg);
+		pll_khz[plls->idx] = phi;
+		printf("%s PLL out frequency: %d.%d Mhz\n",
+				pll_name[plls->idx], phi/1000, phi % 1000);
+		plls++;
+	}
+
+	/* check ARM clock source */
+	reg = readl(PRCM_ARM_CHGCLKREQ_REG);
+	printf("A9 running on %s\n",
+		(reg & 1) ?  "external clock" : "ARM PLL");
+
+	/* go through list of clk_mgt_reg */
+	printf("\n%19s %9s %7s %9s enabled\n",
+			"name(addr)", "value", "PLL", "CLK[MHz]");
+	while (clks->addr) {
+		reg = readl(clks->addr);
+
+		/* convert bit position into array index */
+		clk_sel = ffs((reg >> 5) & 0x7);	/* PLLSW[2:0] */
+
+		if (reg & 0x200)
+			clk_khz = 38400;	/* CLK38 is set */
+		else if ((reg & 0x1f) == 0)
+			/* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
+			clk_khz = 0;
+		else
+			clk_khz = pll_khz[clk_sel] / (reg & 0x1f);
+
+		printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n",
+			clks->descr, clks->addr, reg, pll_name[clk_sel],
+			clk_khz / 1000, clk_khz % 1000,
+			(reg & 0x100) ? "ena" : "dis");
+		clks++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clkinfo,	1,	1,	do_clkinfo,
+	"print clock info",
+	""
+);
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 4e194a2..ab50514 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -171,7 +171,7 @@ int misc_init_r(void)
 {
 	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
 	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
-	struct control_prog_io *prog_io_base = (struct gpio *)OMAP34XX_CTRL_BASE;
+	struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
 
 	/* Enable i2c2 pullup resisters */
 	writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index f8ef4fc..8e6ad74 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -45,9 +45,6 @@ static u32 system_rev;
 
 extern int mx51_fb_init(struct fb_videomode *mode);
 
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-
 static struct fb_videomode nec_nl6448bc26_09c = {
 	"NEC_NL6448BC26-09C",
 	60,	/* Refresh */
@@ -65,6 +62,8 @@ static struct fb_videomode nec_nl6448bc26_09c = {
 	0,	/* flag */
 };
 
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
 void hw_watchdog_reset(void)
 {
 	int val;
@@ -700,47 +699,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	u32 system_rev = get_cpu_rev();
-	u32 cause;
-	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
-
-	puts("Board: TTControl Vision II CPU V");
-
-	switch (system_rev & 0xff) {
-	case CHIP_REV_3_0:
-		puts("3.0 [");
-		break;
-	case CHIP_REV_2_5:
-		puts("2.5 [");
-		break;
-	case CHIP_REV_2_0:
-		puts("2.0 [");
-		break;
-	case CHIP_REV_1_1:
-		puts("1.1 [");
-		break;
-	case CHIP_REV_1_0:
-	default:
-		puts("1.0 [");
-		break;
-	}
-
-	cause = src_regs->srsr;
-	switch (cause) {
-	case 0x0001:
-		puts("POR");
-		break;
-	case 0x0009:
-		puts("RST");
-		break;
-	case 0x0010:
-	case 0x0011:
-		puts("WDOG");
-		break;
-	default:
-		printf("unknown 0x%x", cause);
-	}
-	puts("]\n");
+	puts("Board: TTControl Vision II CPU V\n");
 
 	return 0;
 }