Merge branch 'master' of git://git.denx.de/u-boot-ti

5 files changed, 258 insertions, 80 deletions

diff --git a/board/overo/overo.c b/board/overo/overo.c
index e85be7d..1b67f1f 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -43,6 +43,17 @@
 static void setup_net_chip(void);
 #endif
 
+/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
+static const u32 gpmc_lan_config[] = {
+    NET_LAN9221_GPMC_CONFIG1,
+    NET_LAN9221_GPMC_CONFIG2,
+    NET_LAN9221_GPMC_CONFIG3,
+    NET_LAN9221_GPMC_CONFIG4,
+    NET_LAN9221_GPMC_CONFIG5,
+    NET_LAN9221_GPMC_CONFIG6,
+    /*CONFIG7- computed as params */
+};
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -61,6 +72,70 @@ int board_init(void)
 }
 
 /*
+ * Routine: get_board_revision
+ * Description: Returns the board revision
+ */
+int get_board_revision(void)
+{
+	int revision;
+
+	if (!omap_request_gpio(112) &&
+	    !omap_request_gpio(113) &&
+	    !omap_request_gpio(115)) {
+
+		omap_set_gpio_direction(112, 1);
+		omap_set_gpio_direction(113, 1);
+		omap_set_gpio_direction(115, 1);
+
+		revision = omap_get_gpio_datain(115) << 2 |
+			   omap_get_gpio_datain(113) << 1 |
+			   omap_get_gpio_datain(112);
+
+		omap_free_gpio(112);
+		omap_free_gpio(113);
+		omap_free_gpio(115);
+	} else {
+		printf("Error: unable to acquire board revision GPIOs\n");
+		revision = -1;
+	}
+
+	return revision;
+}
+
+/*
+ * Routine: get_sdio2_config
+ * Description: Return information about the wifi module connection
+ *              Returns 0 if the module connects though a level translator
+ *              Returns 1 if the module connects directly
+ */
+int get_sdio2_config(void)
+{
+	int sdio_direct;
+
+	if (!omap_request_gpio(130) && !omap_request_gpio(139)) {
+
+		omap_set_gpio_direction(130, 0);
+		omap_set_gpio_direction(139, 1);
+
+		sdio_direct = 1;
+		omap_set_gpio_dataout(130, 0);
+		if (omap_get_gpio_datain(139) == 0) {
+			omap_set_gpio_dataout(130, 1);
+			if (omap_get_gpio_datain(139) == 1)
+				sdio_direct = 0;
+		}
+
+		omap_free_gpio(130);
+		omap_free_gpio(139);
+	} else {
+		printf("Error: unable to acquire sdio2 clk GPIOs\n");
+		sdio_direct = -1;
+	}
+
+	return sdio_direct;
+}
+
+/*
  * Routine: misc_init_r
  * Description: Configure board specific parts
  */
@@ -73,6 +148,21 @@ int misc_init_r(void)
 	setup_net_chip();
 #endif
 
+	printf("Board revision: %d\n", get_board_revision());
+
+	switch (get_sdio2_config()) {
+	case 0:
+		printf("Tranceiver detected on mmc2\n");
+		MUX_OVERO_SDIO2_TRANSCEIVER();
+		break;
+	case 1:
+		printf("Direct connection on mmc2\n");
+		MUX_OVERO_SDIO2_DIRECT();
+		break;
+	default:
+		printf("Unable to detect mmc2 connection type\n");
+	}
+
 	dieid_num_r();
 
 	return 0;
@@ -99,14 +189,13 @@ static void setup_net_chip(void)
 {
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
-	/* Configure GPMC registers */
-	writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
-	writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
-	writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
-	writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
-	writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
-	writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
-	writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+	/* first lan chip */
+	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+			GPMC_SIZE_16M);
+
+	/* second lan chip */
+	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
+			GPMC_SIZE_16M);
 
 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
diff --git a/board/overo/overo.h b/board/overo/overo.h
index 1873523..33a92e4 100644
--- a/board/overo/overo.h
+++ b/board/overo/overo.h
@@ -138,7 +138,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
 	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
 								 /* - SMSC911X_NRES*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS3*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | DIS | M4)) /*GPIO_65*/\
  /*DSS*/\
 	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
 	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
@@ -189,18 +189,18 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
 	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M0)) /*CAM_WEN*/\
 	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | EN  | M4)) /*GPIO_112*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | EN  | M4)) /*GPIO_113*/\
 	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | EN  | M4)) /*GPIO_114*/\
 								 /* - PEN_DOWN*/\
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTU | EN  | M4)) /*GPIO_115*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | EN  | M4)) /*GPIO_115*/\
  /*Audio Interface */\
 	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
 	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
 	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
 	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
  /*Expansion card */\
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) /*MMC1_CLK*/\
 	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
 	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
 	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
@@ -211,7 +211,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
 	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
  /*Wireless LAN */\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_130*/\
 	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
 	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
 	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
@@ -220,7 +220,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
 	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
 	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
-	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
  /*Bluetooth*/\
 	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
 	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
@@ -301,7 +301,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M4)) /*GPIO_186*/\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M2)) /*MMC3_CLK*/\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CLK*/\
 	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
 	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | EN  | M4)) /*GPIO_14*/\
 	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | EN  | M4)) /*GPIO_15 - X_GATE*/\
@@ -387,5 +387,36 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
+#define MUX_OVERO_SDIO2_DIRECT() \
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT4*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT5*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT6*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT7*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | EN  | M4)) /*GPIO_126*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_127*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_128*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_129*/
+
+#define MUX_OVERO_SDIO2_TRANSCEIVER() \
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) /*GPIO_126*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_127*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) /*GPIO_128*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_129*/
 
 #endif
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 3b4c9e7..4647908 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -38,8 +38,6 @@
 #include <asm/mach-types.h>
 #include "beagle.h"
 
-static int beagle_revision_c;
-
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -58,43 +56,41 @@ int board_init(void)
 }
 
 /*
- * Routine: beagle_get_revision
- * Description: Return the revision of the BeagleBoard this code is running on.
- *              If it is a revision Ax/Bx board, this function returns 0,
- *              on a revision C board you will get a 1.
+ * Routine: get_board_revision
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ *		C1/2/3, C4 or xM. This can be done by reading
+ *		the level of GPIO173, GPIO172 and GPIO171. This should
+ *		result in
+ *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM
  */
-int beagle_get_revision(void)
+int get_board_revision(void)
 {
-	return beagle_revision_c;
-}
+	int revision;
 
-/*
- * Routine: beagle_identify
- * Description: Detect if we are running on a Beagle revision Ax/Bx or
- *              Cx. This can be done by GPIO_171. If this is low, we are
- *              running on a revision C board.
- */
-void beagle_identify(void)
-{
-	beagle_revision_c = 0;
-	if (!omap_request_gpio(171)) {
-		unsigned int val;
+	if (!omap_request_gpio(171) &&
+	    !omap_request_gpio(172) &&
+	    !omap_request_gpio(173)) {
 
 		omap_set_gpio_direction(171, 1);
-		val = omap_get_gpio_datain(171);
-		omap_free_gpio(171);
+		omap_set_gpio_direction(172, 1);
+		omap_set_gpio_direction(173, 1);
 
-		if (val)
-			beagle_revision_c = 0;
-		else
-			beagle_revision_c = 1;
+		revision = omap_get_gpio_datain(173) << 2 |
+			   omap_get_gpio_datain(172) << 1 |
+			   omap_get_gpio_datain(171);
+
+		omap_free_gpio(171);
+		omap_free_gpio(172);
+		omap_free_gpio(173);
+	} else {
+		printf("Error: unable to acquire board revision GPIOs\n");
+		revision = -1;
 	}
 
-	printf("Board revision ");
-	if (beagle_revision_c)
-		printf("C\n");
-	else
-		printf("Ax/Bx\n");
+	return revision;
 }
 
 /*
@@ -106,6 +102,44 @@ int misc_init_r(void)
 	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
 	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
 
+	switch (get_board_revision()) {
+	case REVISION_AXBX:
+		printf("Beagle Rev Ax/Bx\n");
+		setenv("beaglerev", "AxBx");
+		setenv("mpurate", "600");
+		break;
+	case REVISION_CX:
+		printf("Beagle Rev C1/C2/C3\n");
+		setenv("beaglerev", "Cx");
+		setenv("mpurate", "600");
+		MUX_BEAGLE_C();
+		break;
+	case REVISION_C4:
+		printf("Beagle Rev C4\n");
+		setenv("beaglerev", "C4");
+		setenv("mpurate", "720");
+		MUX_BEAGLE_C();
+		/* Set VAUX2 to 1.8V for EHCI PHY */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		break;
+	case REVISION_XM:
+		printf("Beagle xM Rev A\n");
+		setenv("beaglerev", "xMA");
+		setenv("mpurate", "1000");
+		MUX_BEAGLE_XM();
+		/* Set VAUX2 to 1.8V for EHCI PHY */
+		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+					TWL4030_PM_RECEIVER_DEV_GRP_P1);
+		break;
+	default:
+		printf("Beagle unknown 0x%02x\n", get_board_revision());
+	}
+
 	twl4030_power_init();
 	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
 
@@ -120,8 +154,6 @@ int misc_init_r(void)
 	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
 		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
 
-	beagle_identify();
-
 	dieid_num_r();
 
 	return 0;
@@ -136,8 +168,4 @@ int misc_init_r(void)
 void set_muxconf_regs(void)
 {
 	MUX_BEAGLE();
-
-	if (beagle_revision_c) {
-		MUX_BEAGLE_C();
-	}
 }
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index 7fe6275..d860337 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -33,7 +33,11 @@ const omap3_sysinfo sysinfo = {
 #endif
 };
 
-#define BOARD_REVISION_MASK	(0x1 << 11)
+/* BeagleBoard revisions */
+#define REVISION_AXBX	0x7
+#define REVISION_CX	0x6
+#define REVISION_C4	0x5
+#define REVISION_XM	0x0
 
 /*
  * IEN  - Input Enable
@@ -264,7 +268,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
 	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTU | EN  | M4)) /*GPIO_171*/\
 	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTU | EN  | M4)) /*GPIO_172*/\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTU | EN  | M4)) /*GPIO_173*/\
 	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
 	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
 	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTD | DIS | M4)) /*GPIO_176*/\
@@ -374,11 +378,37 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
 #define MUX_BEAGLE_C() \
-	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTD | DIS | M4)) /*GPIO_140*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IEN | PTD | DIS | M4)) /*GPIO_142*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN | PTD | DIS | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
 	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
 	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
 	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/
 
+#define MUX_BEAGLE_XM() \
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTD | DIS | M4)) /*GPIO_140*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M4)) /*GPIO_142*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_141*/\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M7)) /*safe_mode*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
 #endif
diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda.h
index 8f6a6b1..877ae5f 100644
--- a/board/ti/panda/panda.h
+++ b/board/ti/panda/panda.h
@@ -237,28 +237,28 @@ const struct pad_conf_entry core_padconf_array[] = {
 };
 
 const struct pad_conf_entry wkup_padconf_array[] = {
-	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
-	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_SR_SCL, (PTU | IEN | M0)},	/* sr_scl */
-	{PAD0_SR_SDA, (PTU | IEN | M0)},	/* sr_sda */
-	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
-	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
-	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD1_SYS_32K, (IEN | M0)},		/* sys_32k */
-	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
+	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
+	{PAD1_SR_SCL, (PTU | IEN | M0)},				/* sr_scl */
+	{PAD0_SR_SDA, (PTU | IEN | M0)},				/* sr_sda */
+	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},				/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
+	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
+	{PAD1_SYS_32K, (IEN | M0)},					/* sys_32k */
+	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
 };
 
 #endif