Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	arch/arm/include/asm/mach-types.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

26 files changed, 996 insertions, 142 deletions

diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index ba47ca1..c028a53 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -146,14 +146,7 @@ void mv_phy_88e1121_init(char *name)
 	miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
 
 	/* reset the phy */
-	if (miiphy_read (name, devadr, PHY_BMCR, &reg) != 0) {
-		printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
-		return;
-	}
-	if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) {
-		printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
-		return;
-	}
+	miiphy_reset(name, devadr);
 
 	printf("88E1121 Initialized on %s\n", name);
 }
diff --git a/board/barco/barco.c b/board/barco/barco.c
index d7a0078..c5fe8c4 100644
--- a/board/barco/barco.c
+++ b/board/barco/barco.c
@@ -340,10 +340,6 @@ void serial_puts (const char *c)
 {
 	return;
 }
-void serial_addr (unsigned int i)
-{
-	return;
-}
 int serial_getc (void)
 {
 	return 0;
diff --git a/board/eNET/config.mk b/board/eNET/config.mk
index dcde7fc..63a58fd 100644
--- a/board/eNET/config.mk
+++ b/board/eNET/config.mk
@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0x38040000
+TEXT_BASE = 0x06000000
 CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
 PLATFORM_RELFLAGS += -fvisibility=hidden
 PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 6d0b15a..7f0e257 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/ic/sc520.h>
+#include <net.h>
+#include <netdev.h>
 
 #ifdef CONFIG_HW_WATCHDOG
 #include <watchdog.h>
@@ -43,10 +45,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 
+static void enet_timer_isr(void);
+static void enet_toggle_run_led(void);
+
 void init_sc520_enet (void)
 {
 	/* Set CPU Speed to 100MHz */
-	sc520_mmcr->cpuctl = 0x01;
+	writeb(0x01, &sc520_mmcr->cpuctl);
 
 	/* wait at least one millisecond */
 	asm("movl	$0x2000,%%ecx\n"
@@ -55,7 +60,7 @@ void init_sc520_enet (void)
 	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
-	sc520_mmcr->dbctl = 0x11;
+	writeb(0x11, &sc520_mmcr->dbctl);
 
 	/* turn on the cache and disable write through */
 	asm("movl	%%cr0, %%eax\n"
@@ -70,51 +75,52 @@ int board_early_init_f(void)
 {
 	init_sc520_enet();
 
-	sc520_mmcr->gpcsrt = 0x01;		/* GP Chip Select Recovery Time */
-	sc520_mmcr->gpcspw = 0x07;		/* GP Chip Select Pulse Width */
-	sc520_mmcr->gpcsoff = 0x00;		/* GP Chip Select Offset */
-	sc520_mmcr->gprdw = 0x05;		/* GP Read pulse width */
-	sc520_mmcr->gprdoff = 0x01;		/* GP Read offset */
-	sc520_mmcr->gpwrw = 0x05;		/* GP Write pulse width */
-	sc520_mmcr->gpwroff = 0x01;		/* GP Write offset */
-
-	sc520_mmcr->piodata15_0 = 0x0630;	/* PIO15_PIO0 Data */
-	sc520_mmcr->piodata31_16 = 0x2000;	/* PIO31_PIO16 Data */
-	sc520_mmcr->piodir31_16 = 0x2000;	/* GPIO Direction */
-	sc520_mmcr->piodir15_0 = 0x87b5;	/* GPIO Direction */
-	sc520_mmcr->piopfs31_16 = 0x0dfe;	/* GPIO pin function 31-16 reg */
-	sc520_mmcr->piopfs15_0 = 0x200a;	/* GPIO pin function 15-0 reg */
-	sc520_mmcr->cspfs = 0x00f8;		/* Chip Select Pin Function Select */
-
-	sc520_mmcr->par[2] = 0x200713f8;	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
-	sc520_mmcr->par[3] = 0x2c0712f8;	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
-	sc520_mmcr->par[4] = 0x300711f8;	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
-	sc520_mmcr->par[5] = 0x340710f8;	/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
-	sc520_mmcr->par[6] =  0xe3ffc000;	/* SDRAM (0x00000000, 128MB) */
-	sc520_mmcr->par[7] = 0xaa3fd000;	/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
-	sc520_mmcr->par[8] = 0xca3fd100;	/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
-	sc520_mmcr->par[9] = 0x4203d900;	/* SRAM (GPCS0, 0x19000000, 1MB) */
-	sc520_mmcr->par[10] = 0x4e03d910;	/* SRAM (GPCS3, 0x19100000, 1MB) */
-	sc520_mmcr->par[11] = 0x50018100;	/* DP-RAM (GPCS4, 0x18100000, 4kB) */
-	sc520_mmcr->par[12] = 0x54020000;	/* CFLASH1 (0x200000000, 4kB) */
-	sc520_mmcr->par[13] = 0x5c020001;	/* CFLASH2 (0x200010000, 4kB) */
-/*	sc520_mmcr->par14 = 0x8bfff800; */	/* BOOTCS at  0x18000000 */
-/*	sc520_mmcr->par15 = 0x38201000; */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+	writeb(0x01, &sc520_mmcr->gpcsrt);		/* GP Chip Select Recovery Time */
+	writeb(0x07, &sc520_mmcr->gpcspw);		/* GP Chip Select Pulse Width */
+	writeb(0x00, &sc520_mmcr->gpcsoff);		/* GP Chip Select Offset */
+	writeb(0x05, &sc520_mmcr->gprdw);		/* GP Read pulse width */
+	writeb(0x01, &sc520_mmcr->gprdoff);		/* GP Read offset */
+	writeb(0x05, &sc520_mmcr->gpwrw);		/* GP Write pulse width */
+	writeb(0x01, &sc520_mmcr->gpwroff);		/* GP Write offset */
+
+	writew(0x0630, &sc520_mmcr->piodata15_0);	/* PIO15_PIO0 Data */
+	writew(0x2000, &sc520_mmcr->piodata31_16);	/* PIO31_PIO16 Data */
+	writew(0x2000, &sc520_mmcr->piodir31_16);	/* GPIO Direction */
+	writew(0x87b5, &sc520_mmcr->piodir15_0);	/* GPIO Direction */
+	writew(0x0dfe, &sc520_mmcr->piopfs31_16);	/* GPIO pin function 31-16 reg */
+	writew(0x200a, &sc520_mmcr->piopfs15_0);	/* GPIO pin function 15-0 reg */
+	writeb(0xf8, &sc520_mmcr->cspfs);		/* Chip Select Pin Function Select */
+
+	writel(0x200713f8, &sc520_mmcr->par[2]);	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
+	writel(0x2c0712f8, &sc520_mmcr->par[3]);	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
+	writel(0x300711f8, &sc520_mmcr->par[4]);	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
+	writel(0x340710f8, &sc520_mmcr->par[5]);	/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
+	writel(0xe3ffc000, &sc520_mmcr->par[6]);	/* SDRAM (0x00000000, 128MB) */
+	writel(0xaa3fd000, &sc520_mmcr->par[7]);	/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
+	writel(0xca3fd100, &sc520_mmcr->par[8]);	/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
+	writel(0x4203d900, &sc520_mmcr->par[9]);	/* SRAM (GPCS0, 0x19000000, 1MB) */
+	writel(0x4e03d910, &sc520_mmcr->par[10]);	/* SRAM (GPCS3, 0x19100000, 1MB) */
+	writel(0x50018100, &sc520_mmcr->par[11]);	/* DP-RAM (GPCS4, 0x18100000, 4kB) */
+	writel(0x54020000, &sc520_mmcr->par[12]);	/* CFLASH1 (0x200000000, 4kB) */
+	writel(0x5c020001, &sc520_mmcr->par[13]);	/* CFLASH2 (0x200010000, 4kB) */
+/*	writel(0x8bfff800, &sc520_mmcr->par14); */	/* BOOTCS at  0x18000000 */
+/*	writel(0x38201000, &sc520_mmcr->par15); */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
 
 	/* Disable Watchdog */
-	sc520_mmcr->wdtmrctl = 0x3333;
-	sc520_mmcr->wdtmrctl = 0xcccc;
-	sc520_mmcr->wdtmrctl = 0x0000;
+	writew(0x3333, &sc520_mmcr->wdtmrctl);
+	writew(0xcccc, &sc520_mmcr->wdtmrctl);
+	writew(0x0000, &sc520_mmcr->wdtmrctl);
 
 	/* Chip Select Configuration */
-	sc520_mmcr->bootcsctl = 0x0033;
-	sc520_mmcr->romcs1ctl = 0x0615;
-	sc520_mmcr->romcs2ctl = 0x0615;
+	writew(0x0033, &sc520_mmcr->bootcsctl);
+	writew(0x0615, &sc520_mmcr->romcs1ctl);
+	writew(0x0615, &sc520_mmcr->romcs2ctl);
 
-	sc520_mmcr->adddecctl = 0x02;
-	sc520_mmcr->uart1ctl = 0x07;
-	sc520_mmcr->sysarbctl = 0x06;
-	sc520_mmcr->sysarbmenb = 0x0003;
+	writeb(0x00, &sc520_mmcr->adddecctl);
+	writeb(0x07, &sc520_mmcr->uart1ctl);
+	writeb(0x07, &sc520_mmcr->uart2ctl);
+	writeb(0x06, &sc520_mmcr->sysarbctl);
+	writew(0x0003, &sc520_mmcr->sysarbmenb);
 
 	return 0;
 }
@@ -157,6 +163,10 @@ int last_stage_init(void)
 
 	major = minor = 0;
 
+	outb(0x00, LED_LATCH_ADDRESS);
+
+	register_timer_isr (enet_timer_isr);
+
 	printf("Serck Controls eNET\n");
 
 	return 0;
@@ -172,3 +182,84 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 	} else
 		return 0;
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+void setup_pcat_compatibility()
+{
+	/* disable global interrupt mode */
+	writeb(0x40, &sc520_mmcr->picicr);
+
+	/* set all irqs to edge */
+	writeb(0x00, &sc520_mmcr->pic_mode[0]);
+	writeb(0x00, &sc520_mmcr->pic_mode[1]);
+	writeb(0x00, &sc520_mmcr->pic_mode[2]);
+
+	/*
+	 *  active low polarity on PIC interrupt pins,
+	 *  active high polarity on all other irq pins
+	 */
+	writew(0x0000,&sc520_mmcr->intpinpol);
+
+	/* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */
+	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
+	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
+	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
+
+	/* Disable all other interrupt sources */
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]);	/* disable PCI INT A */
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]);	/* disable PCI INT B */
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]);	/* disable PCI INT C */
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]);	/* disable PCI INT D */
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap);		/* disable DMA INT */
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
+	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
+}
+
+void enet_timer_isr(void)
+{
+	static long enet_ticks = 0;
+
+	enet_ticks++;
+
+	/* Toggle Watchdog every 100ms */
+	if ((enet_ticks % 100) == 0)
+		hw_watchdog_reset();
+
+	/* Toggle Run LED every 500ms */
+	if ((enet_ticks % 500) == 0)
+		enet_toggle_run_led();
+}
+
+void hw_watchdog_reset(void)
+{
+	/* Watchdog Reset must be atomic */
+	long flag = disable_interrupts();
+
+	if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
+		sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
+	else
+		sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
+
+	if (flag)
+		enable_interrupts();
+}
+
+void enet_toggle_run_led(void)
+{
+	unsigned char leds_state= inb(LED_LATCH_ADDRESS);
+	if (leds_state & LED_RUN_BITMASK)
+		outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
+	else
+		outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
+}
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
index e80a8fe..fefb1a4 100644
--- a/board/eNET/eNET_pci.c
+++ b/board/eNET/eNET_pci.c
@@ -93,3 +93,36 @@ void pci_init_board(void)
 {
 	pci_sc520_init(&enet_hose);
 }
+
+int pci_set_regions(struct pci_controller *hose)
+{
+	/* System memory space */
+	pci_set_region(hose->regions + 0,
+		       SC520_PCI_MEMORY_BUS,
+		       SC520_PCI_MEMORY_PHYS,
+		       SC520_PCI_MEMORY_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	/* ISA/PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       SC520_ISA_MEM_BUS,
+		       SC520_ISA_MEM_PHYS,
+		       SC520_ISA_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region(hose->regions + 2,
+		       SC520_PCI_IO_BUS,
+		       SC520_PCI_IO_PHYS,
+		       SC520_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* ISA/PCI I/O space */
+	pci_set_region(hose->regions + 3,
+		       SC520_ISA_IO_BUS,
+		       SC520_ISA_IO_PHYS,
+		       SC520_ISA_IO_SIZE,
+		       PCI_REGION_IO);
+
+	return 4;
+}
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
index 42474a6..dec2cd8 100644
--- a/board/eNET/hardware.h
+++ b/board/eNET/hardware.h
@@ -31,5 +31,6 @@
 #define LED_RX_BITMASK		0x08
 #define LED_TX_BITMASK		0x10
 #define LED_ERR_BITMASK		0x20
+#define WATCHDOG_PIO_BIT	0x8000
 
 #endif /* HARDWARE_H_ */
diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds
index 0d74021..7b0ffaa 100644
--- a/board/eNET/u-boot.lds
+++ b/board/eNET/u-boot.lds
@@ -27,7 +27,7 @@ ENTRY(_start)
 
 SECTIONS
 {
-	. = 0x38040000;		/* Location of bootcode in flash */
+	. = 0x06000000;		/* Location of bootcode in flash */
 	_i386boot_text_start = .;
 	.text  : { *(.text); }
 
@@ -97,14 +97,13 @@ SECTIONS
 	 * at reset and the code have to fit.
 	 * The fff0 offset of resetvec is important, however.
 	 */
-
 	. = 0xfffffe00;
-	.start32 : AT (0x3807fe00) { *(.start32); }
+	.start32 : AT (0x0603fe00) { *(.start32); }
 
 	. = 0xf800;
-	.start16 : AT (0x3807f800) { *(.start16); }
+	.start16 : AT (0x0603f800) { *(.start16); }
 
 	. = 0xfff0;
-	.resetvec : AT (0x3807fff0) { *(.resetvec); }
+	.resetvec : AT (0x0603fff0) { *(.resetvec); }
 	_i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
 }
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 2ae4cbd..a199d46 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -1090,3 +1090,15 @@ U_BOOT_CMD(
 	"Show Marvell strapping register",
 	"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)"
 );
+
+int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pldver, 1, 1, do_pldver,
+	"Show PLD version",
+	"Show PLD version)");
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 4c03630..5347958 100644
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -538,14 +538,14 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 			break;
 /*------------------------------------------------------------------------------------------------------------------------------*/
 
-#ifdef CONFIG_ECC
+#ifdef CONFIG_MV64360_ECC
 		case 11:	/* Error Check Type */
 			dimmInfo->errorCheckType = data[i];
 			DP (printf
 			    ("Error Check Type (0=NONE):			%d\n",
 			     dimmInfo->errorCheckType));
 			break;
-#endif
+#endif /* of ifdef CONFIG_MV64360_ECC */
 /*------------------------------------------------------------------------------------------------------------------------------*/
 
 		case 12:	/* Refresh Interval */
@@ -1254,6 +1254,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 	ulong tmp;
 	ulong tmp_sdram_mode = 0;	/* 0x141c */
 	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
 	int i;
 
 	/* sanity checking */
@@ -1269,7 +1270,6 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 		DP (printf
 		    ("Module is registered, but we do not support registered Modules !!!\n"));
 
-
 	/* delay line */
 	set_dfcdlInit ();	/* may be its not needed */
 	DP (printf ("Delay line set done\n"));
@@ -1281,8 +1281,16 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
 	}
 
+#ifdef CONFIG_MV64360_ECC
+	if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
+		/* DRAM has ECC, so turn it on */
+		sdram_config_reg |= BIT18;
+		DP(printf("Enabling ECC\n"));
+	}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
 	/* SDRAM configuration */
-	GT_REG_WRITE (SDRAM_CONFIG, 0x58200400);
+	GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
 	DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
 
 	/* SDRAM open pages controll keep open as much as I can */
@@ -1598,7 +1606,84 @@ dram_size(long int *base, long int maxsize)
     return maxsize;
 }
 
-/* ------------------------------------------------------------------------- */
+#ifdef CONFIG_MV64360_ECC
+/*
+ * mv_dma_is_channel_active:
+ * Checks if a engine is busy.
+ */
+int mv_dma_is_channel_active(int engine)
+{
+	ulong data;
+
+	data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
+	if (data & BIT14)	/* activity status */
+		return 1;
+
+	return 0;
+}
+
+/*
+ * mv_dma_set_memory_space:
+ * Set a DMA memory window for the DMA's address decoding map.
+ */
+int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
+			    ulong mem_space_attr, ulong base_address,
+			    ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (base_address % size != 0)
+		return 0;
+
+	if (size >= 0x10000) {
+		size &= 0xffff0000;
+		base_address = (base_address & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
+			     (base_address | mem_space_target |
+			      mem_space_attr));
+		GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
+			     (size - 1) & 0xffff0000);
+		temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
+			     (temp & ~(BIT0 << mem_space)));
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*
+ * mv_dma_transfer:
+ * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
+ */
+int mv_dma_transfer(int engine, ulong source_addr,
+		    ulong dest_addr, ulong bytes, ulong command)
+{
+	ulong eng_off_reg;	/* Engine Offset Register */
+
+	if (bytes > 0xffff)
+		command = command | BIT31;	 /* DMA_16M_DESCRIPTOR_MODE */
+
+	command = command | ((command >> 6) & 0x7);
+	eng_off_reg = engine * 4;
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
+		     bytes);
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
+		     source_addr);
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
+		     dest_addr);
+	command |= BIT12	/* DMA_CHANNEL_ENABLE */
+		| BIT9;		/* DMA_NON_CHAIN_MODE */
+
+	/* Activate DMA engine By writting to mv_dma_control_register */
+	GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
+
+	return 1;
+}
+#endif /* of ifdef CONFIG_MV64360_ECC */
 
 /* ppcboot interface function to SDRAM init - this is where all the
  * controlling logic happens */
@@ -1607,10 +1692,13 @@ initdram(int board_type)
 {
 	int s0 = 0, s1 = 0;
 	int checkbank[4] = { [0 ... 3] = 0 };
-		ulong bank_no, realsize, total, check;
+	ulong realsize, total, check;
 	AUX_MEM_DIMM_INFO dimmInfo1;
 	AUX_MEM_DIMM_INFO dimmInfo2;
-	int nhr;
+	int bank_no, nhr;
+#ifdef CONFIG_MV64360_ECC
+	ulong dest, mem_space_attr;
+#endif /* of ifdef CONFIG_MV64360_ECC */
 
 	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
 
@@ -1668,6 +1756,28 @@ initdram(int board_type)
 		realsize = dram_size((long int *)total, check);
 		memory_map_bank(bank_no, total, realsize);
 
+#ifdef CONFIG_MV64360_ECC
+		if (((dimmInfo1.errorCheckType != 0) &&
+		     ((dimmInfo2.errorCheckType != 0) ||
+		      (dimmInfo2.numOfModuleBanks == 0))) &&
+		    (CPCI750_ECC_TEST)) {
+			printf("ECC Initialization of Bank %d:", bank_no);
+			mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
+			mv_dma_set_memory_space(0, 0, mem_space_attr, total,
+						realsize);
+			for (dest = total; dest < total + realsize;
+			     dest += _8M) {
+				mv_dma_transfer(0, total, dest, _8M,
+						BIT8 |	/* DMA_DTL_128BYTES */
+						BIT3 |	/* DMA_HOLD_SOURCE_ADDR */
+						BIT11);	/* DMA_BLOCK_TRANSFER_MODE */
+				while (mv_dma_is_channel_active(0))
+					;
+			}
+			printf(" PASS\n");
+		}
+#endif /* of ifdef CONFIG_MV64360_ECC */
+
 		total += realsize;
 	}
 
@@ -1700,3 +1810,30 @@ int set_dfcdlInit (void)
 
 	return (0);
 }
+
+int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int ecc_counter;
+	unsigned int ecc_addr;
+
+	GT_REG_READ(0x1458, &ecc_counter);
+	GT_REG_READ(0x1450, &ecc_addr);
+	GT_REG_WRITE(0x1450, 0);
+
+	printf("Error Counter since Reset:  %8d\n", ecc_counter);
+	printf("Last error address       :0x%08x (" , ecc_addr & 0xfffffff8);
+	if (ecc_addr & 0x01)
+		printf("double");
+	else
+		printf("single");
+	printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
+
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	show_ecc, 1, 1, do_show_ecc,
+	"Show Marvell MV64360 ECC Info",
+	"Show Marvell MV64360 ECC Counter and last error."
+);
diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk
index 0fb4efa..0a4dbaa 100644
--- a/board/esd/plu405/config.mk
+++ b/board/esd/plu405/config.mk
@@ -25,4 +25,4 @@
 # esd PLU405 boards
 #
 
-TEXT_BASE = 0xFFFA0000
+TEXT_BASE = 0xFFF80000
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 620eb16..df289aa 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -29,18 +29,18 @@ endif
 
 LIB	= $(obj)lib$(VENDOR).a
 
-COBJS-${CONFIG_FSL_CADMUS}	+= cadmus.o
-COBJS-${CONFIG_FSL_VIA}		+= cds_via.o
-COBJS-${CONFIG_FSL_DIU_FB}	+= fsl_diu_fb.o fsl_logo_bmp.o
-COBJS-${CONFIG_FSL_PIXIS}	+= pixis.o
-COBJS-${CONFIG_FSL_NGPIXIS}	+= ngpixis.o
-COBJS-${CONFIG_PQ_MDS_PIB}	+= pq-mds-pib.o
-COBJS-${CONFIG_ID_EEPROM}	+= sys_eeprom.o
-COBJS-${CONFIG_FSL_SGMII_RISER}	+= sgmii_riser.o
+COBJS-$(CONFIG_FSL_CADMUS)	+= cadmus.o
+COBJS-$(CONFIG_FSL_VIA)		+= cds_via.o
+COBJS-$(CONFIG_FSL_DIU_FB)	+= fsl_diu_fb.o fsl_logo_bmp.o
+COBJS-$(CONFIG_FSL_PIXIS)	+= pixis.o
+COBJS-$(CONFIG_FSL_NGPIXIS)	+= ngpixis.o
+COBJS-$(CONFIG_PQ_MDS_PIB)	+= pq-mds-pib.o
+COBJS-$(CONFIG_ID_EEPROM)	+= sys_eeprom.o
+COBJS-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
 
-COBJS-${CONFIG_MPC8541CDS}	+= cds_pci_ft.o
-COBJS-${CONFIG_MPC8548CDS}	+= cds_pci_ft.o
-COBJS-${CONFIG_MPC8555CDS}	+= cds_pci_ft.o
+COBJS-$(CONFIG_MPC8541CDS)	+= cds_pci_ft.o
+COBJS-$(CONFIG_MPC8548CDS)	+= cds_pci_ft.o
+COBJS-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
 
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index cbee8fe..e740ad8 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007, 2010 Freescale Semiconductor, Inc.
  * York Sun <yorksun@freescale.com>
  *
  * FSL DIU Framebuffer driver
@@ -26,6 +26,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <malloc.h>
+#include <asm/io.h>
 
 #include "fsl_diu_fb.h"
 
@@ -267,9 +268,9 @@ int fsl_diu_init(int xres,
 
 	memset(info->screen_base, 0, info->smem_len);
 
-	dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
-	dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
-	dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
+	out_be32(&dr.diu_reg->desc[0], (int)&dummy_ad);
+	out_be32(&dr.diu_reg->desc[1], (int)&dummy_ad);
+	out_be32(&dr.diu_reg->desc[2], (int)&dummy_ad);
 	debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
 	debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
 
@@ -331,26 +332,26 @@ int fsl_diu_init(int xres,
 
 	/* Program DIU registers */
 
-	hw->gamma = (unsigned int) gamma.paddr;
-	hw->cursor= (unsigned int) cursor.paddr;
-	hw->bgnd = 0x007F7F7F;				/* BGND */
-	hw->bgnd_wb = 0;				/* BGND_WB */
-	hw->disp_size = var->yres << 16 | var->xres;	/* DISP SIZE */
-	hw->wb_size = 0;				/* WB SIZE */
-	hw->wb_mem_addr = 0;				/* WB MEM ADDR */
-	hw->hsyn_para = var->left_margin << 22 |	/* BP_H */
+	out_be32(&hw->gamma, (int)gamma.paddr);
+	out_be32(&hw->cursor, (int)cursor.paddr);
+	out_be32(&hw->bgnd, 0x007F7F7F);
+	out_be32(&hw->bgnd_wb, 0);				/* BGND_WB */
+	out_be32(&hw->disp_size, var->yres << 16 | var->xres);	/* DISP SIZE */
+	out_be32(&hw->wb_size, 0);				/* WB SIZE */
+	out_be32(&hw->wb_mem_addr, 0);				/* WB MEM ADDR */
+	out_be32(&hw->hsyn_para, var->left_margin << 22 |	/* BP_H */
 			var->hsync_len << 11   |	/* PW_H */
-			var->right_margin;		/* FP_H */
-	hw->vsyn_para = var->upper_margin << 22 |	/* BP_V */
-			var->vsync_len << 11    |	/* PW_V  */
-			var->lower_margin;		/* FP_V  */
+			var->right_margin);		/* FP_H */
 
-	hw->syn_pol = 0;			/* SYNC SIGNALS POLARITY */
-	hw->thresholds = 0x00037800;		/* The Thresholds */
-	hw->int_status = 0;			/* INTERRUPT STATUS */
-	hw->int_mask = 0;			/* INT MASK */
-	hw->plut = 0x01F5F666;
+	out_be32(&hw->vsyn_para, var->upper_margin << 22 |	/* BP_V */
+			var->vsync_len << 11    |	/* PW_V  */
+			var->lower_margin);		/* FP_V  */
 
+	out_be32(&hw->syn_pol, 0);			/* SYNC SIGNALS POLARITY */
+	out_be32(&hw->thresholds, 0x00037800);		/* The Thresholds */
+	out_be32(&hw->int_status, 0);			/* INTERRUPT STATUS */
+	out_be32(&hw->int_mask, 0);			/* INT MASK */
+	out_be32(&hw->plut, 0x01F5F666);
 	/* Pixel Clock configuration */
 	debug("DIU pixclock in ps - %d\n", var->pixclock);
 	diu_set_pixel_clock(var->pixclock);
@@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info)
 	struct diu_ad *ad = &fsl_diu_fb_ad;
 
 	debug("Entered: enable_panel\n");
-	if (hw->desc[0] != (unsigned int)ad)
-		hw->desc[0] = (unsigned int)ad;
+	if (in_be32(&hw->desc[0]) != (unsigned)ad)
+		out_be32(&hw->desc[0], (unsigned)ad);
 	debug("desc[0] = 0x%x\n", hw->desc[0]);
 	return 0;
 }
@@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info)
 	struct diu *hw = dr.diu_reg;
 
 	debug("Entered: disable_panel\n");
-	if (hw->desc[0] != (unsigned int)&dummy_ad)
-		hw->desc[0] = (unsigned int)&dummy_ad;
+	if (in_be32(&hw->desc[0]) != (unsigned)&dummy_ad)
+		out_be32(&hw->desc[0], (unsigned)&dummy_ad);
 	return 0;
 }
 
@@ -443,7 +444,7 @@ static void enable_lcdc(void)
 
 	debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
 	if (!fb_enabled) {
-		hw->diu_mode = dr.mode;
+		out_be32(&hw->diu_mode, dr.mode);
 		fb_enabled++;
 	}
 	debug("diu_mode = %d\n", hw->diu_mode);
@@ -455,7 +456,7 @@ static void disable_lcdc(void)
 
 	debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
 	if (fb_enabled) {
-		hw->diu_mode = 0;
+		out_be32(&hw->diu_mode, 0);
 		fb_enabled = 0;
 	}
 }
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index 1f11563..61b7454 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -28,15 +28,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 253ed18..1968106 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,6 +30,7 @@
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
+#include <asm/fsl_serdes.h>
 #include <spd.h>
 #include <miiphy.h>
 #include <libfdt.h>
@@ -219,9 +220,13 @@ void pci_init_board(void)
 
 	puts("\n");
 #ifdef CONFIG_PCIE3
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+	pcie_configured = is_serdes_configured(PCIE3);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
+				LAW_TRGT_IF_PCIE_3);
+		set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_3);
 		SET_STD_PCIE_INFO(pci_info[num], 3);
 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 		printf ("    PCIE3 connected to Slot3 as %s (base address %lx)\n",
@@ -239,9 +244,13 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE1
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+	pcie_configured = is_serdes_configured(PCIE1);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
+				LAW_TRGT_IF_PCIE_1);
+		set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_1);
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot1 as %s (base address %lx)\n",
@@ -259,9 +268,13 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE2
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+	pcie_configured = is_serdes_configured(PCIE2);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+		set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
+				LAW_TRGT_IF_PCIE_2);
+		set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCIE_2);
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf ("    PCIE2 connected to Slot 2 as %s (base address %lx)\n",
@@ -285,6 +298,10 @@ void pci_init_board(void)
 	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
+				LAW_TRGT_IF_PCI);
+		set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
+				LAW_TRGT_IF_PCI);
 		SET_STD_PCI_INFO(pci_info[num], 1);
 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
 		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
@@ -481,17 +498,6 @@ get_board_ddr_clk(ulong dummy)
 }
 #endif
 
-int sata_initialize(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	uint sdrs2_io_sel =
-		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
-	if (sdrs2_io_sel & 0x04)
-		return 1;
-
-	return __sata_initialize();
-}
-
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_TSEC_ENET
@@ -540,15 +546,23 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_PCI1
 	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci0", NULL);
 #endif
 #ifdef CONFIG_PCIE2
 	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci1", NULL);
 #endif
 #ifdef CONFIG_PCIE2
 	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci2", NULL);
 #endif
 #ifdef CONFIG_PCIE1
 	ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
+#else
+	ft_fsl_pci_setup(blob, "pci3", NULL);
 #endif
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
index 930a206..847edaf 100644
--- a/board/freescale/mpc8610hpcd/Makefile
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -27,7 +27,7 @@ COBJS-y	+= $(BOARD).o
 COBJS-$(CONFIG_FSL_DDR2) += ddr.o
 COBJS-y	+= law.o
 
-COBJS-${CONFIG_FSL_DIU_FB}	+= mpc8610hpcd_diu.o
+COBJS-$(CONFIG_FSL_DIU_FB)	+= mpc8610hpcd_diu.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/korat/korat.c b/board/korat/korat.c
index d5260dc..e5ec694 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007-2009
+ * (C) Copyright 2007-2010
  * Larry Johnson, lrj@acm.org
  *
  * (C) Copyright 2006-2007
@@ -417,7 +417,7 @@ int misc_init_r(void)
 		 * then connect the CompactFlash controller to the PowerPC USB
 		 * port.
 		 */
-		printf("Attaching CompactFalsh controller to PPC USB\n");
+		printf("Attaching CompactFlash controller to PPC USB\n");
 		out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
 		      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
 	} else {
@@ -425,7 +425,7 @@ int misc_init_r(void)
 			printf("Warning: \"korat_usbcf\" is not set to a legal "
 			       "value (\"ppc\" or \"pci\")\n");
 
-		printf("Attaching CompactFalsh controller to PCI USB\n");
+		printf("Attaching CompactFlash controller to PCI USB\n");
 	}
 	if (act == NULL || strcmp(act, "hostdev") == 0) {
 		/* SDR Setting */
diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile
index 504935f..12c7cb6 100644
--- a/board/matrix_vision/mvblm7/Makefile
+++ b/board/matrix_vision/mvblm7/Makefile
@@ -32,12 +32,13 @@ SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
+	@mkimage -T script -C none -n M7_script -d bootscript $(obj)bootscript.img
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
 
 distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
+	rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
 
 #########################################################################
 
diff --git a/board/matrix_vision/mvblm7/mvblm7_autoscript b/board/matrix_vision/mvblm7/bootscript
index dc385fd..dc385fd 100644
--- a/board/matrix_vision/mvblm7/mvblm7_autoscript
+++ b/board/matrix_vision/mvblm7/bootscript
diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile
index b179e6d..2817fe0 100644
--- a/board/matrix_vision/mvsmr/Makefile
+++ b/board/matrix_vision/mvsmr/Makefile
@@ -36,13 +36,13 @@ SOBJS   := $(addprefix $(obj),$(SOBJS))
 
 $(LIB): $(obj).depend $(OBJS)
 	        $(AR) $(ARFLAGS) $@ $(OBJS)
-	@mkimage -T script -C none -n mvSMR_Script -d bootscript bootscript.img
+	@mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
 
 distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
+	rm -f $(LIB) core *.bak $(obj).depend $(obj)bootscript.img
 
 #########################################################################
 
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
index 3e917a9..f9b103e 100644
--- a/board/matrix_vision/mvsmr/u-boot.lds
+++ b/board/matrix_vision/mvsmr/u-boot.lds
@@ -55,11 +55,11 @@ SECTIONS
   {
     /* WARNING - the following is hand-optimized to fit within  */
     /* the first two sectors (=8KB) of our S29GL flash chip */
-    arch/powerpc/cpu/mpc5xxx/start.o          (.text)
-    arch/powerpc/cpu/mpc5xxx/traps.o          (.text)
-    lib/crc32.o         (.text)
-    arch/powerpc/lib/cache.o             (.text)
-    arch/powerpc/lib/time.o              (.text)
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text)
+    arch/powerpc/cpu/mpc5xxx/traps.o	(.text)
+    lib/crc32.o				(.text)
+    arch/powerpc/lib/cache.o		(.text)
+    arch/powerpc/lib/time.o		(.text)
 
     /* This is only needed to force failure if size of above code will ever */
     /* increase and grow into reserved space. */
diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile
new file mode 100644
index 0000000..dad0457
--- /dev/null
+++ b/board/mosaixtech/icon/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2009-2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+SOBJS	= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mosaixtech/icon/chip_config.c b/board/mosaixtech/icon/chip_config.c
new file mode 100644
index 0000000..b9dd447
--- /dev/null
+++ b/board/mosaixtech/icon/chip_config.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+	{
+		"400-133", "CPU: 400 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"500-166", "CPU: 500 PLB: 166 OPB:  83 EBC:  83",
+		{ 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"533-133", "CPU: 533 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"667-133", "CPU: 667 PLB: 133 OPB:  66 EBC:  66",
+		{ 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"667-166", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
+		{ 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
+	},
+	{
+		"800-160", "CPU: 800 PLB: 160 OPB:  53 EBC:  17",
+		{ 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
+	},
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/mosaixtech/icon/config.mk b/board/mosaixtech/icon/config.mk
new file mode 100644
index 0000000..b2748ce
--- /dev/null
+++ b/board/mosaixtech/icon/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2009-2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFA0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c
new file mode 100644
index 0000000..fbace9e
--- /dev/null
+++ b/board/mosaixtech/icon/icon.c
@@ -0,0 +1,319 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	unsigned long mfr;
+
+	/*
+	 * Interrupt controller setup for the ICON 440SPe board.
+	 *
+	 *--------------------------------------------------------------------
+	 * IRQ    | Source                            | Pol.  | Sensi.| Crit.
+	 *--------+-----------------------------------+-------+-------+-------
+	 * IRQ 00 | UART0                             | High  | Level | Non
+	 * IRQ 01 | UART1                             | High  | Level | Non
+	 * IRQ 02 | IIC0                              | High  | Level | Non
+	 * IRQ 03 | IIC1                              | High  | Level | Non
+	 * IRQ 04 | PCI0X0 MSG IN                     | High  | Level | Non
+	 * IRQ 05 | PCI0X0 CMD Write                  | High  | Level | Non
+	 * IRQ 06 | PCI0X0 Power Mgt                  | High  | Level | Non
+	 * IRQ 07 | PCI0X0 VPD Access                 | Rising| Edge  | Non
+	 * IRQ 08 | PCI0X0 MSI level 0                | High  | Lvl/ed| Non
+	 * IRQ 09 | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non
+	 * IRQ 10 | UIC2 Non-critical Int.            | NA    | NA    | Non
+	 * IRQ 11 | UIC2 Critical Interrupt           | NA    | NA    | Crit
+	 * IRQ 12 | PCI Express MSI Level 0           | Rising| Edge  | Non
+	 * IRQ 13 | PCI Express MSI Level 1           | Rising| Edge  | Non
+	 * IRQ 14 | PCI Express MSI Level 2           | Rising| Edge  | Non
+	 * IRQ 15 | PCI Express MSI Level 3           | Rising| Edge  | Non
+	 * IRQ 16 | UIC3 Non-critical Int.            | NA    | NA    | Non
+	 * IRQ 17 | UIC3 Critical Interrupt           | NA    | NA    | Crit
+	 * IRQ 18 | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non
+	 * IRQ 19 | DMA Channel 0 FIFO Full           | High  | Level | Non
+	 * IRQ 20 | DMA Channel 0 Stat FIFO           | High  | Level | Non
+	 * IRQ 21 | DMA Channel 1 FIFO Full           | High  | Level | Non
+	 * IRQ 22 | DMA Channel 1 Stat FIFO           | High  | Level | Non
+	 * IRQ 23 | I2O Inbound Doorbell              | High  | Level | Non
+	 * IRQ 24 | Inbound Post List FIFO Not Empt   | High  | Level | Non
+	 * IRQ 25 | I2O Region 0 LL PLB Write         | High  | Level | Non
+	 * IRQ 26 | I2O Region 1 LL PLB Write         | High  | Level | Non
+	 * IRQ 27 | I2O Region 0 HB PLB Write         | High  | Level | Non
+	 * IRQ 28 | I2O Region 1 HB PLB Write         | High  | Level | Non
+	 * IRQ 29 | GPT Down Count Timer              | Rising| Edge  | Non
+	 * IRQ 30 | UIC1 Non-critical Int.            | NA    | NA    | Non
+	 * IRQ 31 | UIC1 Critical Interrupt           | NA    | NA    | Crit.
+	 *--------------------------------------------------------------------
+	 * IRQ 32 | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non
+	 * IRQ 33 | MAL Serr                          | High  | Level | Non
+	 * IRQ 34 | MAL Txde                          | High  | Level | Non
+	 * IRQ 35 | MAL Rxde                          | High  | Level | Non
+	 * IRQ 36 | DMC CE or DMC UE                  | High  | Level | Non
+	 * IRQ 37 | EBC or UART2                      | High  |Lvl Edg| Non
+	 * IRQ 38 | MAL TX EOB                        | High  | Level | Non
+	 * IRQ 39 | MAL RX EOB                        | High  | Level | Non
+	 * IRQ 40 | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non
+	 * IRQ 41 | PCIX0 MSI level 2                 | High  |Lvl Edg| Non
+	 * IRQ 42 | PCIX0 MSI level 3                 | High  |Lvl Edg| Non
+	 * IRQ 43 | L2 Cache                          | Risin | Edge  | Non
+	 * IRQ 44 | GPT Compare Timer 0               | Risin | Edge  | Non
+	 * IRQ 45 | GPT Compare Timer 1               | Risin | Edge  | Non
+	 * IRQ 46 | GPT Compare Timer 2               | Risin | Edge  | Non
+	 * IRQ 47 | GPT Compare Timer 3               | Risin | Edge  | Non
+	 * IRQ 48 | GPT Compare Timer 4               | Risin | Edge  | Non
+	 * IRQ 49 | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non
+	 * IRQ 50 | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non
+	 * IRQ 51 | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non
+	 * IRQ 52 | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non
+	 * IRQ 53 | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non
+	 * IRQ 54 | DMA Error                         | High  | Level | Non
+	 * IRQ 55 | DMA I2O Error                     | High  | Level | Non
+	 * IRQ 56 | Serial ROM                        | High  | Level | Non
+	 * IRQ 57 | PCIX0 Error                       | High  | Edge  | Non
+	 * IRQ 58 | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non
+	 * IRQ 59 | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non
+	 * IRQ 60 | EMAC0 Interrupt                   | High  | Level | Non
+	 * IRQ 61 | EMAC0 Wake-up                     | High  | Level | Non
+	 * IRQ 62 | Reserved                          | High  | Level | Non
+	 * IRQ 63 | XOR                               | High  | Level | Non
+	 *--------------------------------------------------------------------
+	 * IRQ 64 | PE0 AL                            | High  | Level | Non
+	 * IRQ 65 | PE0 VPD Access                    | Risin | Edge  | Non
+	 * IRQ 66 | PE0 Hot Reset Request             | Risin | Edge  | Non
+	 * IRQ 67 | PE0 Hot Reset Request             | Falli | Edge  | Non
+	 * IRQ 68 | PE0 TCR                           | High  | Level | Non
+	 * IRQ 69 | PE0 BusMaster VCO                 | Falli | Edge  | Non
+	 * IRQ 70 | PE0 DCR Error                     | High  | Level | Non
+	 * IRQ 71 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 72 | PE1 AL                            | High  | Level | Non
+	 * IRQ 73 | PE1 VPD Access                    | Risin | Edge  | Non
+	 * IRQ 74 | PE1 Hot Reset Request             | Risin | Edge  | Non
+	 * IRQ 75 | PE1 Hot Reset Request             | Falli | Edge  | Non
+	 * IRQ 76 | PE1 TCR                           | High  | Level | Non
+	 * IRQ 77 | PE1 BusMaster VCO                 | Falli | Edge  | Non
+	 * IRQ 78 | PE1 DCR Error                     | High  | Level | Non
+	 * IRQ 79 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 80 | PE2 AL                            | High  | Level | Non
+	 * IRQ 81 | PE2 VPD Access                    | Risin | Edge  | Non
+	 * IRQ 82 | PE2 Hot Reset Request             | Risin | Edge  | Non
+	 * IRQ 83 | PE2 Hot Reset Request             | Falli | Edge  | Non
+	 * IRQ 84 | PE2 TCR                           | High  | Level | Non
+	 * IRQ 85 | PE2 BusMaster VCO                 | Falli | Edge  | Non
+	 * IRQ 86 | PE2 DCR Error                     | High  | Level | Non
+	 * IRQ 87 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 88 | External IRQ(5)                   | Progr | Progr | Non
+	 * IRQ 89 | External IRQ 4 - Ethernet         | Progr | Progr | Non
+	 * IRQ 90 | External IRQ 3 - PCI-X            | Progr | Progr | Non
+	 * IRQ 91 | External IRQ 2 - PCI-X            | Progr | Progr | Non
+	 * IRQ 92 | External IRQ 1 - PCI-X            | Progr | Progr | Non
+	 * IRQ 93 | External IRQ 0 - PCI-X            | Progr | Progr | Non
+	 * IRQ 94 | Reserved                          | N/A   | N/A   | Non
+	 * IRQ 95 | Reserved                          | N/A   | N/A   | Non
+	 *--------------------------------------------------------------------
+	 * IRQ 96 | PE0 INTA                          | High  | Level | Non
+	 * IRQ 97 | PE0 INTB                          | High  | Level | Non
+	 * IRQ 98 | PE0 INTC                          | High  | Level | Non
+	 * IRQ 99 | PE0 INTD                          | High  | Level | Non
+	 * IRQ 100| PE1 INTA                          | High  | Level | Non
+	 * IRQ 101| PE1 INTB                          | High  | Level | Non
+	 * IRQ 102| PE1 INTC                          | High  | Level | Non
+	 * IRQ 103| PE1 INTD                          | High  | Level | Non
+	 * IRQ 104| PE2 INTA                          | High  | Level | Non
+	 * IRQ 105| PE2 INTB                          | High  | Level | Non
+	 * IRQ 106| PE2 INTC                          | High  | Level | Non
+	 * IRQ 107| PE2 INTD                          | Risin | Edge  | Non
+	 * IRQ 108| PCI Express MSI Level 4           | Risin | Edge  | Non
+	 * IRQ 109| PCI Express MSI Level 5           | Risin | Edge  | Non
+	 * IRQ 110| PCI Express MSI Level 6           | Risin | Edge  | Non
+	 * IRQ 111| PCI Express MSI Level 7           | Risin | Edge  | Non
+	 * IRQ 116| PCI Express MSI Level 12          | Risin | Edge  | Non
+	 * IRQ 112| PCI Express MSI Level 8           | Risin | Edge  | Non
+	 * IRQ 113| PCI Express MSI Level 9           | Risin | Edge  | Non
+	 * IRQ 114| PCI Express MSI Level 10          | Risin | Edge  | Non
+	 * IRQ 115| PCI Express MSI Level 11          | Risin | Edge  | Non
+	 * IRQ 117| PCI Express MSI Level 13          | Risin | Edge  | Non
+	 * IRQ 118| PCI Express MSI Level 14          | Risin | Edge  | Non
+	 * IRQ 119| PCI Express MSI Level 15          | Risin | Edge  | Non
+	 * IRQ 120| PCI Express MSI Level 16          | Risin | Edge  | Non
+	 * IRQ 121| PCI Express MSI Level 17          | Risin | Edge  | Non
+	 * IRQ 122| PCI Express MSI Level 18          | Risin | Edge  | Non
+	 * IRQ 123| PCI Express MSI Level 19          | Risin | Edge  | Non
+	 * IRQ 124| PCI Express MSI Level 20          | Risin | Edge  | Non
+	 * IRQ 125| PCI Express MSI Level 21          | Risin | Edge  | Non
+	 * IRQ 126| PCI Express MSI Level 22          | Risin | Edge  | Non
+	 * IRQ 127| PCI Express MSI Level 23          | Risin | Edge  | Non
+	 */
+
+	/*
+	 * Put UICs in PowerPC 440SPe mode.
+	 * Initialise UIC registers. Clear all interrupts. Disable all
+	 * interrupts. Set critical interrupt values. Set interrupt polarities.
+	 * Set interrupt trigger levels. Make bit 0 High priority. Clear all
+	 * interrupts again.
+	 */
+	mtdcr(UIC3SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all interrupts */
+	mtdcr(UIC3CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC3PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr(UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC3SR, 0x00000000);	/* clear all  interrupts*/
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all  interrupts*/
+
+	mtdcr(UIC2SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr(UIC2CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC2PR, 0xebebebff);	/* Set Interrupt Polarities*/
+	mtdcr(UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC2SR, 0x00000000);	/* clear all interrupts */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* Clear all interrupts*/
+	mtdcr(UIC1ER, 0x00000000);	/* disable all interrupts*/
+	mtdcr(UIC1CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels*/
+	mtdcr(UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC1SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all interrupts*/
+
+	mtdcr(UIC0SR, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all int. excepted cascade */
+	mtdcr(UIC0CR, 0x00104001);	/* Set Critical / Non Critical IRQs */
+	mtdcr(UIC0PR, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr(UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr(UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
+	mtdcr(UIC0SR, 0x00000000);	/* clear all interrupts*/
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all interrupts*/
+
+	mfsdr(SDR0_MFR, mfr);
+	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
+	mtsdr(SDR0_MFR, mfr);
+
+	mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
+
+	out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
+	out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
+	out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+	 * boot EBC mapping only supports a maximum of 16MBytes
+	 * (4.ff00.0000 - 4.ffff.ffff).
+	 * To solve this problem, the FLASH has to get remapped to another
+	 * EBC address which accepts bigger regions:
+	 *
+	 * 0xfc00.0000 -> 4.ec00.0000
+	 */
+
+	/* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
+	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
+
+	/* Remove TLB entry of boot EBC mapping */
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+	/* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+		    CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+	/*
+	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+	 * 0xfc00.0000 is possible
+	 */
+
+	/*
+	 * Clear potential errors resulting from auto-calibration.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: ICON");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ *
+ * Tested successfully with the following SODIMM:
+ * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
+ *
+ * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
+ * directly after power-up. Only after running for more than 10 minutes
+ * real stable auto-calibration windows could be found.
+ */
+u32 ddr_wrdtr(u32 default_val)
+{
+	return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
+}
+
+u32 ddr_clktr(u32 default_val)
+{
+	return SDRAM_CLKTR_CLKP_180_DEG_ADV;
+}
+
+/*
+ * Override the weak default implementation and return the
+ * last PCIe slot number (max number - 1).
+ */
+int board_pcie_last(void)
+{
+	/* Only 2 PCIe ports used on ICON, so the last one is 1 */
+	return 1;
+}
diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S
new file mode 100644
index 0000000..70ed6ce
--- /dev/null
+++ b/board/mosaixtech/icon/init.S
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ */
+
+	.section .bootpg,"ax"
+
+	.globl tlbtab
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+	 * use the speed up boot process. It is patched after relocation to
+	 * enable SA_I.
+	 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+		 4, AC_RWX | SA_G) /* TLB 0 */
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
+		 AC_RWX | SA_I)
+
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
+		 AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
+		 CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
+		 AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
+		 AC_RW | SA_IG)
+
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,
+		 AC_RW | SA_IG)
+	tlbtab_end
diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c
index 1044de2..cb30b48 100644
--- a/board/sheldon/simpc8313/simpc8313.c
+++ b/board/sheldon/simpc8313/simpc8313.c
@@ -29,16 +29,17 @@
 #include <mpc83xx.h>
 #include <ns16550.h>
 #include <nand.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_NAND_SPL
 int checkboard(void)
 {
 	puts("Board: Sheldon Instruments SIMPC8313\n");
 	return 0;
 }
 
-#ifndef CONFIG_NAND_SPL
 static struct pci_region pci_regions[] = {
 	{
 		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
@@ -91,6 +92,40 @@ void pci_init_board(void)
 int misc_init_r(void)
 {
 	int rc = 0;
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	fsl_lbus_t *lbus = &immap->lbus;
+	u32 *mxmr = &lbus->mamr;	/* Pointer to mamr */
+
+	/* UPM Table Configuration Code */
+	static uint UPMATable[] = {
+		/* Read Single-Beat (RSS) */
+		0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Read Burst (RBS) */
+		0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
+		0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Write Single-Beat (WSS) */
+		0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Write Burst (WBS) */
+		0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
+		0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
+		0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Refresh Timer (RTS) */
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		/* Exception Condition (EXS) */
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
+	};
+
+	upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
+
+	/* Set LUPWAIT to be active low and enabled */
+	out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
 
 	return rc;
 }