Coding Style cleanup

Signed-off-by: Wolfgang Denk <wd@denx.de>

5 files changed, 15 insertions, 20 deletions

diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
index 9e73c57..dcb91bd 100644
--- a/board/bct-brettl2/cled.c
+++ b/board/bct-brettl2/cled.c
@@ -13,7 +13,7 @@
 
 int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong addr = 0x20000000 + 0x200000; // AMS2
+	ulong addr = 0x20000000 + 0x200000; /* AMS2 */
 	uchar data;
 
 	if (argc < 2)
diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c
index f865eb4..656d5cd 100644
--- a/board/davedenx/qong/fpga.c
+++ b/board/davedenx/qong/fpga.c
@@ -92,4 +92,3 @@ int qong_fpga_init(void)
 }
 
 #endif
-
diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
index 35865e0..019f93f 100644
--- a/board/isee/igep0030/config.mk
+++ b/board/isee/igep0030/config.mk
@@ -31,4 +31,3 @@
 
 # For use with external or internal boots.
 TEXT_BASE = 0x80008000
-
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
index b7fa695..36e9146 100644
--- a/board/xes/common/fsl_8xxx_misc.c
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -52,11 +52,9 @@ uint get_board_derivative(void)
 #endif
 
        /*
-        * The top 4 lines of the local bus address are pulled low/high and
-        * can be read to determine the least significant digit of a board's
-        * model number.
-        */
+	* The top 4 lines of the local bus address are pulled low/high and
+	* can be read to determine the least significant digit of a board's
+	* model number.
+	*/
        return gur->gpporcr >> 28;
 }
-
-
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index 718cd98..38a4597 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -55,16 +55,16 @@ unsigned int fsl_ddr_get_mem_data_rate(void)
  *     There are traditionally three board-specific SDRAM timing parameters
  *     which must be calculated based on the particular PCB artwork.  These are:
  *     1.) CPO (Read Capture Delay)
- *             - TIMING_CFG_2 register
- *             Source: Calculation based on board trace lengths and
- *                     chip-specific internal delays.
+ *	       - TIMING_CFG_2 register
+ *	       Source: Calculation based on board trace lengths and
+ *		       chip-specific internal delays.
  *     2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- *             - DDR_SDRAM_CLK_CNTL register
- *             Source: Signal Integrity Simulations
+ *	       - DDR_SDRAM_CLK_CNTL register
+ *	       Source: Signal Integrity Simulations
  *     3.) 2T Timing on Addr/Ctl
- *             - TIMING_CFG_2 register
- *             Source: Signal Integrity Simulations
- *             Usually only needed with heavy load/very high speed (>DDR2-800)
+ *	       - TIMING_CFG_2 register
+ *	       Source: Signal Integrity Simulations
+ *	       Usually only needed with heavy load/very high speed (>DDR2-800)
  *
  *     ====== XPedite550x DDR3-800 read delay calculations ======
  *
@@ -82,14 +82,14 @@ typedef struct {
 const board_specific_parameters_t board_specific_parameters[][20] = {
 	{
 		/* Controller 0 */
-                {
+		{
 			/* DDR3-600/667 */
 			.datarate_mhz_low	= 500,
 			.datarate_mhz_high	= 750,
 			.clk_adjust		= 5,
 			.cpo			= 31,
 		},
-                {
+		{
 			/* DDR3-800 */
 			.datarate_mhz_low	= 750,
 			.datarate_mhz_high	= 850,
@@ -162,4 +162,3 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->rtt_override = 1;
 	popts->rtt_override_value = 3;
 }
-