Merge branch 'for-wd-master' of git://git.denx.de/u-boot-pxa

71 files changed, 206 insertions, 7848 deletions

diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile
index a806b18..b111b51 100644
--- a/board/cerf250/Makefile
+++ b/board/cerf250/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= cerf250.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c
index 59346bc..043afea 100644
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of cerf PXA Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
@@ -58,19 +59,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/cerf250/config.mk b/board/cerf250/config.mk
deleted file mode 100644
index c2d46b2..0000000
--- a/board/cerf250/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Cerf board with PXA250 cpu
-#
-#
-CONFIG_SYS_TEXT_BASE = 0xa3080000
diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S
deleted file mode 100644
index 5bfe53c..0000000
--- a/board/cerf250/lowlevel_init.S
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr	r0, =GPSR0
-	ldr	r1, =CONFIG_SYS_GPSR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPSR1
-	ldr	r1, =CONFIG_SYS_GPSR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPSR2
-	ldr	r1, =CONFIG_SYS_GPSR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR0
-	ldr	r1, =CONFIG_SYS_GPCR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR1
-	ldr	r1, =CONFIG_SYS_GPCR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPCR2
-	ldr	r1, =CONFIG_SYS_GPCR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR0
-	ldr	r1, =CONFIG_SYS_GPDR0_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR1
-	ldr	r1, =CONFIG_SYS_GPDR1_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GPDR2
-	ldr	r1, =CONFIG_SYS_GPDR2_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR0_L
-	ldr	r1, =CONFIG_SYS_GAFR0_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR0_U
-	ldr	r1, =CONFIG_SYS_GAFR0_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR1_L
-	ldr	r1, =CONFIG_SYS_GAFR1_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR1_U
-	ldr	r1, =CONFIG_SYS_GAFR1_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR2_L
-	ldr	r1, =CONFIG_SYS_GAFR2_L_VAL
-	str	r1, [r0]
-
-	ldr	r0, =GAFR2_U
-	ldr	r1, =CONFIG_SYS_GAFR2_U_VAL
-	str	r1, [r0]
-
-	ldr	r0, =PSSR			/* enable GPIO pins */
-	ldr	r1, =CONFIG_SYS_PSSR_VAL
-	str	r1, [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
-						/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-
-	ldr	r1, =MEMC_BASE			/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC0_VAL
-	str	r2, [r1, #MSC0_OFFSET]
-	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC1_VAL
-	str	r2, [r1, #MSC1_OFFSET]
-	ldr	r2, [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr	r2, =CONFIG_SYS_MSC2_VAL
-	str	r2, [r1, #MSC2_OFFSET]
-	ldr	r2, [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr	r2, =CONFIG_SYS_MECR_VAL
-	str	r2, [r1, #MECR_OFFSET]
-	ldr	r2, [r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr	r2, =CONFIG_SYS_MCMEM0_VAL
-	str	r2, [r1, #MCMEM0_OFFSET]
-	ldr	r2, [r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr	r2, =CONFIG_SYS_MCMEM1_VAL
-	str	r2, [r1, #MCMEM1_OFFSET]
-	ldr	r2, [r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr	r2, =CONFIG_SYS_MCATT0_VAL
-	str	r2, [r1, #MCATT0_OFFSET]
-	ldr	r2, [r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr	r2, =CONFIG_SYS_MCATT1_VAL
-	str	r2, [r1, #MCATT1_OFFSET]
-	ldr	r2, [r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr	r2, =CONFIG_SYS_MCIO0_VAL
-	str	r2, [r1, #MCIO0_OFFSET]
-	ldr	r2, [r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr	r2, =CONFIG_SYS_MCIO1_VAL
-	str	r2, [r1, #MCIO1_OFFSET]
-	ldr	r2, [r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field, set SDRAM clocks free running */
-
-	ldr	r3, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =0xFFF
-	and	r3, r3,  r2
-
-	ldr	r0, [r1, #MDREFR_OFFSET]
-	bic	r0, r0, r2
-	bic	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
-	orr	r0, r0, r3
-
-	str	r0, [r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
-					MDREFR_K2RUN |MDREFR_K2DB2)
-	and	r4, r4, r2
-	bic	r0, r0, r2
-	orr	r0, r0, r4
-
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r0, r0, #(MDREFR_SLFRSH)
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
-
-	ldr     r4, =CONFIG_SYS_MDREFR_VAL
-	ldr	r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
-			MDREFR_K1FREE | MDREFR_K2FREE)
-	and	r4, r4, r2
-	orr	r0, r0, r4
-	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r0, [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4, =CONFIG_SYS_MDCNFG_VAL
-	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
-	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4, [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
-						/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3, =CONFIG_SYS_DRAM_BASE
-.rept 8
-	str	r2, [r3]
-.endr
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3, [r1, #MDCNFG_OFFSET]
-	orr	r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2, =CONFIG_SYS_MDMRS_VAL
-	str     r2, [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2, =ICLR
-	str     r1, [r2]
-
-	ldr     r2, =ICMR	/* mask all interrupts at the controller    */
-	str     r1, [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1, =CKEN
-	mov     r2, #0
-	str     r2, [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1, =CCCR
-	str     r2, [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1, =OSCC
-	mov     r2, #OSCC_OON
-	str     r2, [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-	ldr     r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR /* enable no sources */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov     pc, lr
diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile
index ae570e1..f8b44ab 100644
--- a/board/colibri_pxa270/Makefile
+++ b/board/colibri_pxa270/Makefile
@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= colibri_pxa270.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
index 8aa7067..191fb33 100644
--- a/board/colibri_pxa270/colibri_pxa270.c
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -42,8 +42,9 @@ struct serial_device *default_serial_console (void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of vpac270 */
 	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
@@ -54,13 +55,18 @@ int board_init (void)
 	return 0;
 }
 
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
 #ifdef	CONFIG_CMD_USB
diff --git a/board/colibri_pxa270/config.mk b/board/colibri_pxa270/config.mk
deleted file mode 100644
index 0f10662..0000000
--- a/board/colibri_pxa270/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000
diff --git a/board/colibri_pxa270/lowlevel_init.S b/board/colibri_pxa270/lowlevel_init.S
deleted file mode 100644
index a43dac2..0000000
--- a/board/colibri_pxa270/lowlevel_init.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Toradex Colibri PXA270 Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr
diff --git a/board/cradle/Makefile b/board/cradle/Makefile
index 1ae785d..720593c 100644
--- a/board/cradle/Makefile
+++ b/board/cradle/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= cradle.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/cradle/config.mk b/board/cradle/config.mk
deleted file mode 100644
index 6656bdd..0000000
--- a/board/cradle/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa0f80000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index c4a93f9..2bbf2d5 100644
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -185,6 +185,10 @@ int
 board_init (void)
 /**********************************************************/
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	led_code (0xf, YELLOW);
 
 	/* arch number of HHP Cradle */
@@ -206,24 +210,18 @@ board_init (void)
 	return 1;
 }
 
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
-
-	return (PHYS_SDRAM_1_SIZE +
-		PHYS_SDRAM_2_SIZE +
-		PHYS_SDRAM_3_SIZE +
-		PHYS_SDRAM_4_SIZE );
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
deleted file mode 100644
index 39964b6..0000000
--- a/board/cradle/lowlevel_init.S
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-   .macro SET_LED val
-   ldr   r6, =GPCR2
-   ldr   r7, =0
-   str   r7, [r6]
-   ldr   r6, =GPSR2
-   ldr   r7, =\val
-   str   r7, [r6]
-   .endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-    /* Set up GPIO pins first */
-
-   ldr      r0,   =GPSR0
-   ldr      r1,   =CONFIG_SYS_GPSR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPSR1
-   ldr      r1,   =CONFIG_SYS_GPSR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPSR2
-   ldr      r1,   =CONFIG_SYS_GPSR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR0
-   ldr      r1,   =CONFIG_SYS_GPCR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR1
-   ldr      r1,   =CONFIG_SYS_GPCR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPCR2
-   ldr      r1,   =CONFIG_SYS_GPCR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER0
-   ldr      r1,   =CONFIG_SYS_GRER0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER1
-   ldr      r1,   =CONFIG_SYS_GRER1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GRER2
-   ldr      r1,   =CONFIG_SYS_GRER2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER0
-   ldr      r1,   =CONFIG_SYS_GFER0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER1
-   ldr      r1,   =CONFIG_SYS_GFER1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GFER2
-   ldr      r1,   =CONFIG_SYS_GFER2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR0
-   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR1
-   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GPDR2
-   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR0_L
-   ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR0_U
-   ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR1_L
-   ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR1_U
-   ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR2_L
-   ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
-   str      r1,   [r0]
-
-   ldr      r0,   =GAFR2_U
-   ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
-   str      r1,   [r0]
-
-   /* enable GPIO pins */
-   ldr      r0,   =PSSR
-   ldr      r1,   =CONFIG_SYS_PSSR_VAL
-   str      r1,   [r0]
-
-   SET_LED 1
-
-   ldr    r3, =MSC1             /* low - bank 2 Lubbock Registers / SRAM */
-   ldr    r2, =CONFIG_SYS_MSC1_VAL     /* high - bank 3 Ethernet Controller */
-   str    r2, [r3]              /* need to set MSC1 before trying to write to the HEX LEDs */
-   ldr    r2, [r3]              /* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
-    Initlialize Memory Controller
-
-    See PXA250 Operating System Developer's Guide
-
-    pause for 200 uSecs- allow internal clocks to settle
-    *Note: only need this if hard reset... doing it anyway for now
-*/
-
-    @ Step 1
-   @ ---- Wait 200 usec
-   ldr r3, =OSCR       @ reset the OS Timer Count to zero
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300         @ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-   SET_LED 2
-
-mem_init:
-	@ get memory controller base address
-	ldr     r1,  =MEMC_BASE
-
-
-@****************************************************************************
-@  Step 2
-@
-
-   @ Step 2a
-   @ write msc0, read back to ensure data latches
-   @
-   ldr     r2,   =CONFIG_SYS_MSC0_VAL
-   str     r2,   [r1, #MSC0_OFFSET]
-   ldr     r2,   [r1, #MSC0_OFFSET]
-
-   @ write msc1
-   ldr     r2,  =CONFIG_SYS_MSC1_VAL
-   str     r2,  [r1, #MSC1_OFFSET]
-   ldr     r2,  [r1, #MSC1_OFFSET]
-
-   @ write msc2
-   ldr     r2,  =CONFIG_SYS_MSC2_VAL
-   str     r2,  [r1, #MSC2_OFFSET]
-   ldr     r2,  [r1, #MSC2_OFFSET]
-
-   @ Step 2b
-   @ write mecr
-   ldr     r2,  =CONFIG_SYS_MECR_VAL
-   str     r2,  [r1, #MECR_OFFSET]
-
-   @ write mcmem0
-   ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-   str     r2,  [r1, #MCMEM0_OFFSET]
-
-   @ write mcmem1
-   ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-   str     r2,  [r1, #MCMEM1_OFFSET]
-
-   @ write mcatt0
-   ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-   str     r2,  [r1, #MCATT0_OFFSET]
-
-   @ write mcatt1
-   ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-   str     r2,  [r1, #MCATT1_OFFSET]
-
-   @ write mcio0
-   ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-   str     r2,  [r1, #MCIO0_OFFSET]
-
-   @ write mcio1
-   ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-   str     r2,  [r1, #MCIO1_OFFSET]
-
-   /*SET_LED 3 */
-
-   @ Step 2c
-   @ fly-by-dma is defeatured on this part
-   @ write flycnfg
-   @ldr     r2,  =CONFIG_SYS_FLYCNFG_VAL
-   @str     r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-   @ Step 2d
-   @ get the mdrefr settings
-   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
-
-   @ extract DRI field (we need a valid DRI field)
-   @
-   ldr     r2,  =0xFFF
-
-   @ valid DRI field in r3
-   @
-   and     r3,  r3,  r2
-
-   @ get the reset state of MDREFR
-   @
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ clear the DRI field
-   @
-   bic     r4,  r4,  r2
-
-   @ insert the valid DRI field loaded above
-   @
-   orr     r4,  r4,  r3
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ *Note: preserve the mdrefr value in r4 *
-
-   /*SET_LED 4 */
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-   mov   pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-   @ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-   @ clear the free-running clock bits
-   @ (clear K0Free, K1Free, K2Free
-   @
-   bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-   @ set K0RUN for CPLD clock
-   @
-   orr   r4,  r4,  #0x00002000
-
-   @ set K1RUN if bank 0 installed
-   @
-   orr   r4,  r4,  #0x00010000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ deassert SLFRSH
-   @
-   bic     r4,  r4,  #0x00400000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ assert E1PIN
-   @
-   orr     r4,  r4,  #0x00008000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-   nop
-   nop
-#else
-   @ Step 2d
-   @ get the mdrefr settings
-   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @  Step 4
-
-   @ set K0RUN for CPLD clock
-   @
-   orr   r4,  r4,  #0x00002000
-
-   @ set K1RUN for bank 0
-   @
-   orr   r4,  r4,  #0x00010000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-
-   @ deassert SLFRSH
-   @
-   bic     r4,  r4,  #0x00400000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-
-   @ assert E1PIN
-   @
-   orr     r4,  r4,  #0x00008000
-
-   @ write back mdrefr
-   @
-   str     r4,  [r1, #MDREFR_OFFSET]
-   ldr     r4,  [r1, #MDREFR_OFFSET]
-   nop
-   nop
-#endif
-
-   @ Step 4d
-   @ fetch platform value of mdcnfg
-   @
-   ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-   @ disable all sdram banks
-   @
-   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-   @ program banks 0/1 for bus width
-   @
-   bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
-
-   @ write initial value of mdcnfg, w/o enabling sdram banks
-   @
-   str     r2,  [r1, #MDCNFG_OFFSET]
-
-   @ Step 4e
-   @ pause for 200 uSecs
-   @
-   ldr r3, =OSCR       @ reset the OS Timer Count to zero
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-   /*SET_LED 5 */
-
-   /* Why is this here??? */
-   mov    r0, #0x78                @turn everything off
-   mcr    p15, 0, r0, c1, c0, 0      @(caches off, MMU off, etc.)
-
-   @ Step 4f
-   @ Access memory *not yet enabled* for CBR refresh cycles (8)
-   @ - CBR is generated for all banks
-
-   ldr     r2, =CONFIG_SYS_DRAM_BASE
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-
-   @ Step 4g
-   @get memory controller base address
-   @
-   ldr     r1,  =MEMC_BASE
-
-   @fetch current mdcnfg value
-   @
-   ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-   @enable sdram bank 0 if installed (must do for any populated bank)
-   @
-   orr     r3,  r3,  #MDCNFG_DE0
-
-   @write back mdcnfg, enabling the sdram bank(s)
-   @
-   str     r3,  [r1, #MDCNFG_OFFSET]
-
-   @ Step 4h
-   @ write mdmrs
-   @
-   ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-   str     r2,  [r1, #MDMRS_OFFSET]
-
-   @ Done Memory Init
-
-   /*SET_LED 6 */
-
-   @********************************************************************
-   @ Disable (mask) all interrupts at the interrupt controller
-   @
-
-   @ clear the interrupt level register (use IRQ, not FIQ)
-   @
-   mov     r1, #0
-   ldr     r2,  =ICLR
-   str     r1,  [r2]
-
-   @ Set interrupt mask register
-   @
-   ldr     r1,  =CONFIG_SYS_ICMR_VAL
-   ldr     r2,  =ICMR
-   str     r1,  [r2]
-
-   @ ********************************************************************
-   @ Disable the peripheral clocks, and set the core clock
-   @
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-   ldr     r1,  =CKEN
-   mov     r2,  #0
-   str     r2,  [r1]
-
-   @ set core clocks
-   @
-   ldr     r2,  =CONFIG_SYS_CCCR_VAL
-   ldr     r1,  =CCCR
-   str     r2,  [r1]
-
-#ifdef ENABLE32KHZ
-   @ enable the 32Khz oscillator for RTC and PowerManager
-   @
-   ldr     r1,  =OSCC
-   mov     r2,  #OSCC_OON
-   str     r2,  [r1]
-
-   @ NOTE:  spin here until OSCC.OOK get set,
-   @        meaning the PLL has settled.
-   @
-60:
-   ldr     r2, [r1]
-   ands    r2, r2, #1
-   beq     60b
-#endif
-
-	@ Turn on needed clocks
-	@
-   ldr     r1,  =CKEN
-   ldr     r2,  =CONFIG_SYS_CKEN_VAL
-   str     r2,  [r1]
-
-   /*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-   /*Disable software and data breakpoints */
-   mov   r0,#0
-   mcr   p15,0,r0,c14,c8,0  /* ibcr0 */
-   mcr   p15,0,r0,c14,c9,0  /* ibcr1 */
-   mcr   p15,0,r0,c14,c4,0  /* dbcon */
-
-   /*Enable all debug functionality */
-   mov   r0,#0x80000000
-   mcr   p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-   /*SET_LED 8 */
-
-   mov   pc, r10
-
-@ End lowlevel_init
diff --git a/board/csb226/Makefile b/board/csb226/Makefile
index c12dbea..5e1332b 100644
--- a/board/csb226/Makefile
+++ b/board/csb226/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= csb226.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/csb226/config.mk b/board/csb226/config.mk
deleted file mode 100644
index 9e46555..0000000
--- a/board/csb226/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index 6eed9ad..dd29e62 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -69,8 +69,9 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of CSB226 board */
 	gd->bd->bi_arch_number = MACH_TYPE_CSB226;
@@ -82,21 +83,20 @@ int board_init (void)
 }
 
 
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
-
 /**
  * csb226_set_led: - switch LEDs on or off
  *
diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S
deleted file mode 100644
index 55169be..0000000
--- a/board/csb226/lowlevel_init.S
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
-/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
-/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/*	ldr	r1,	=LED_BLANK */
-/*	mov	r0,	#0xFF */
-/*	str	r0,	[r1]		/  turn on hex leds */
-/* */
-/*loop: */
-/* */
-/*   ldr	r0, =0xB0070001 */
-/*   ldr	r1, =_LED */
-/*   str	r0, [r1]		/  hex display */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
-	adr	r3, mem_init		/* r0 <- current position of code   */
-	ldr	r2, =mem_init
-	cmp	r3, r2			/* skip init if in place            */
-	beq	initirqs
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	ldr	r2,	=0xFFF
-	and	r3,	r3, r2
-	ldr	r4,	=0x03ca4000
-	orr	r4,	r4,  r3
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,	[r1, #MDREFR_OFFSET]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* Step 4a: assert MDREFR:K?RUN and configure                       */
-	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
-
-	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4, #(MDREFR_SLFRSH)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
-
-	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	/*          There should 9 writes, since the first write doesn't    */
-	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
-	/*          PXA210 Processors Specification Update,                 */
-	/*          Jan 2003, Errata #116, page 30.                         */
-
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr	r3, [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str	r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-/*
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-*/
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size                                                  */
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR			/* enable no sources        */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#ifndef DEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr
diff --git a/board/delta/Makefile b/board/delta/Makefile
deleted file mode 100644
index 648e00c..0000000
--- a/board/delta/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= delta.o nand.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/delta/config.mk b/board/delta/config.mk
deleted file mode 100644
index 8b24044..0000000
--- a/board/delta/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x83008000
diff --git a/board/delta/delta.c b/board/delta/delta.c
deleted file mode 100644
index df23076..0000000
--- a/board/delta/delta.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <da9030.h>
-#include <malloc.h>
-#include <command.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static void init_DA9030(void);
-static void keys_init(void);
-static void get_pressed_keys(uchar *s);
-static uchar *key_match(uchar *kbd_data);
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
-
-	/* arch number of Lubbock-Board mk@tbd: fix this! */
-	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef DELTA_CHECK_KEYBD
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	char *str;
-	int i;
-#endif /* DELTA_CHECK_KEYBD */
-
-	setenv("stdout", "serial");
-	setenv("stderr", "serial");
-
-#ifdef DELTA_CHECK_KEYBD
-	keys_init();
-
-	memset(kbd_data, '\0', KEYBD_DATALEN);
-
-	/* check for pressed keys and setup keybd_env */
-	get_pressed_keys(kbd_data);
-
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-	}
-	setenv ("keybd", keybd_env);
-
-	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
-
-# ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
-	setenv ("preboot", str);	/* set or delete definition */
-# endif /* CONFIG_PREBOOT */
-	if (str != NULL) {
-		free (str);
-	}
-#endif /* DELTA_CHECK_KEYBD */
-
-	init_DA9030();
-	return 0;
-}
-
-/*
- * Magic Key Handling, mainly copied from board/lwmon/lwmon.c
- */
-#ifdef DELTA_CHECK_KEYBD
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-/*
- * Get pressed keys
- * s is a buffer of size KEYBD_DATALEN-1
- */
-static void get_pressed_keys(uchar *s)
-{
-	unsigned long val;
-	val = readl(GPLR3);
-
-	if(val & (1<<31))
-		*s++ = KEYBD_KP_DKIN0;
-	if(val & (1<<18))
-		*s++ = KEYBD_KP_DKIN1;
-	if(val & (1<<29))
-		*s++ = KEYBD_KP_DKIN2;
-	if(val & (1<<22))
-		*s++ = KEYBD_KP_DKIN5;
-}
-
-static void keys_init()
-{
-	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
-	udelay(100);
-
-	/* Configure GPIOs */
-	writel(0xa840, GPIO127);	/* KP_DKIN0 */
-	writel(0xa840, GPIO114);	/* KP_DKIN1 */
-	writel(0xa840, GPIO125);	/* KP_DKIN2 */
-	writel(0xa840, GPIO118);	/* KP_DKIN5 */
-
-	/* Configure GPIOs as inputs */
-	writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
-	writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
-
-	udelay(100);
-}
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
-	/* uchar compare[KEYBD_DATALEN-1]; */
-	uchar compare[KEYBD_DATALEN];
-	char *nxt;
-	int i;
-
-	/* Don't include modifier byte */
-	/* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */
-	memcpy (compare, kbd_data, KEYBD_DATALEN);
-
-	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
-		uchar c;
-		int k;
-
-		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
-		if (str == (uchar *)nxt) {	/* invalid character */
-			break;
-		}
-
-		/*
-		 * Check if this key matches the input.
-		 * Set matches to zero, so they match only once
-		 * and we can find duplicates or extra keys
-		 */
-		for (k = 0; k < sizeof(compare); ++k) {
-			if (compare[k] == '\0')	/* only non-zero entries */
-				continue;
-			if (c == compare[k]) {	/* found matching key */
-				compare[k] = '\0';
-				break;
-			}
-		}
-		if (k == sizeof(compare)) {
-			return -1;		/* unmatched key */
-		}
-	}
-
-	/*
-	 * A full match leaves no keys in the `compare' array,
-	 */
-	for (i = 0; i < sizeof(compare); ++i) {
-		if (compare[i])
-		{
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-
-static uchar *key_match (uchar *kbd_data)
-{
-	char magic[sizeof (kbd_magic_prefix) + 1];
-	uchar *suffix;
-	char *kbd_magic_keys;
-
-	/*
-	 * The following string defines the characters that can pe appended
-	 * to "key_magic" to form the names of environment variables that
-	 * hold "magic" key codes, i. e. such key codes that can cause
-	 * pre-boot actions. If the string is empty (""), then only
-	 * "key_magic" is checked (old behaviour); the string "125" causes
-	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
-	 */
-	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
-		kbd_magic_keys = "";
-
-	/* loop over all magic keys;
-	 * use '\0' suffix in case of empty string
-	 */
-	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
-		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-#if 0
-		printf ("### Check magic \"%s\"\n", magic);
-#endif
-		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
-			char cmd_name[sizeof (kbd_command_prefix) + 1];
-			char *cmd;
-
-			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
-			cmd = getenv (cmd_name);
-#if 0
-			printf ("### Set PREBOOT to $(%s): \"%s\"\n",
-				cmd_name, cmd ? cmd : "<<NULL>>");
-#endif
-			*kbd_data = *suffix;
-			return ((uchar *)cmd);
-		}
-	}
-#if 0
-	printf ("### Delete PREBOOT\n");
-#endif
-	*kbd_data = '\0';
-	return (NULL);
-}
-
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	int i;
-
-	/* Read keys */
-	get_pressed_keys(kbd_data);
-	puts ("Keys:");
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-		printf (" %02x", kbd_data[i]);
-	}
-	putc ('\n');
-	setenv ("keybd", keybd_env);
-	return 0;
-}
-
-U_BOOT_CMD(
-	   kbd,	1,	1,	do_kbd,
-	   "read keyboard status",
-	   ""
-);
-
-#endif /* DELTA_CHECK_KEYBD */
-
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
-}
-
-void i2c_init_board()
-{
-	writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
-
-	/* setup I2C GPIO's */
-	writel(0x801, GPIO32);		/* SCL = Alt. Fkt. 1 */
-	writel(0x801, GPIO33);		/* SDA = Alt. Fkt. 1 */
-}
-
-/* initialize the DA9030 Power Controller */
-static void init_DA9030()
-{
-	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-
-	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
-	udelay(100);
-
-	/* Rising Edge on EXTON to reset DA9030 */
-	writel(0x8800, GPIO17);	/* configure GPIO17, no pullup, -down */
-	writel(readl(GPDR0) | (1<<17), GPDR0);	/* GPIO17 is output */
-	writel((1<<17), GSDR0);
-	writel((1<<17), GPCR0);	/* drive GPIO17 low */
-	writel((1<<17), GPSR0);	/* drive GPIO17 high */
-
-#if CONFIG_SYS_DA9030_EXTON_DELAY
-	udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY);	/* wait for DA9030 */
-#endif
-	writel((1<<17), GPCR0);	/* drive GPIO17 low */
-
-	/* reset the watchdog and go active (0xec) */
-	val = (SYS_CONTROL_A_HWRES_ENABLE |
-	       (0x6<<4) |
-	       SYS_CONTROL_A_WDOG_ACTION |
-	       SYS_CONTROL_A_WATCHDOG);
-	if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) {
-		printf("Error accessing DA9030 via i2c.\n");
-		return;
-	}
-
-	val = 0x80;
-	if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
-		printf("Error accessing DA9030 via i2c.\n");
-		return;
-	}
-
-	i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
-	i2c_reg_write(addr, LDO2_3, 0xd1);	/* LDO2 =1,9V, LDO3=3,1V */
-	i2c_reg_write(addr, LDO4_5, 0xcc);	/* LDO2 =1,9V, LDO3=3,1V */
-	i2c_reg_write(addr, LDO6_SIMCP, 0x3e);	/* LDO6=3,2V, SIMCP = 5V support */
-	i2c_reg_write(addr, LDO7_8, 0xc9);	/* LDO7=2,7V, LDO8=3,0V */
-	i2c_reg_write(addr, LDO9_12, 0xec);	/* LDO9=3,0V, LDO12=3,2V */
-	i2c_reg_write(addr, BUCK, 0x0c);	/* Buck=1.2V */
-	i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
-	i2c_reg_write(addr, LDO_10_11, 0xcc);	/* LDO10=3.0V  LDO11=3.0V */
-	i2c_reg_write(addr, LDO_15, 0xae);	/* LDO15=1.8V, dislock first 3bit */
-	i2c_reg_write(addr, LDO_14_16, 0x05);	/* LDO14=2.8V, LDO16=NB */
-	i2c_reg_write(addr, LDO_18_19, 0x9c);	/* LDO18=3.0V, LDO19=2.7V */
-	i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
-	i2c_reg_write(addr, BUCK2_DVC1, 0x9a);	/* Buck2=1.5V plus Update support of 520 MHz */
-	i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
-	i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
-	i2c_reg_write(addr, USBPUMP, 0xc1);	/* start pump, ignore HW signals */
-
-	val = i2c_reg_read(addr, STATUS);
-	if(val & STATUS_CHDET)
-		printf("Charger detected, turning on LED.\n");
-	else {
-		printf("No charger detetected.\n");
-		/* undervoltage? print error and power down */
-	}
-}
-
-
-#if 0
-/* reset the DA9030 watchdog */
-void hw_watchdog_reset(void)
-{
-	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
-	val = i2c_reg_read(addr, SYS_CONTROL_A);
-	val |= SYS_CONTROL_A_WATCHDOG;
-	i2c_reg_write(addr, SYS_CONTROL_A, val);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
deleted file mode 100644
index 1664f3b..0000000
--- a/board/delta/lowlevel_init.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-.macro wait time
-	ldr		r2, =OSCR
-	mov		r3, #0
-	str		r3, [r2]
-0:
-	ldr		r3, [r2]
-	cmp		r3, \time
-	bls		0b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Set up GPIO pins first */
-	mov	 r10, lr
-
-	/*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
-	ldr		r0, =GPIO97
-	ldr		r1, =0x801
-	str		r1, [r0]
-
-	ldr		r0, =GPIO98
-	ldr		r1, =0x801
-	str		r1, [r0]
-
-	/* tebrandt - ASCR, clear the RDH bit */
-	ldr		r0, =ASCR
-	ldr		r1, [r0]
-	bic		r1, r1, #0x80000000
-	str		r1, [r0]
-
-mem_init:
-	/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
-	ldr		r0, =ACCR
-	ldr		r1, [r0]
-	orr		r1, r1, #0x3000
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
-	ldr		r0, =MDCNFG
-	ldr		r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
-	/* ldr		r1, =0x80000403 */
-	str		r1, [r0]
-	ldr		r1, [r0]	/* delay until written */
-
-	/* 3. wait nop power up waiting period (200ms)
-	 * optimization: Steps 4+6 can be done during this
-	 */
-	wait #0x300
-
-	/* 4. Perform an initial Rcomp-calibration cycle */
-	ldr		r0, =RCOMP
-	ldr		r1, =0x80000000
-	str		r1, [r0]
-	ldr		r1, [r0]	/* delay until written */
-	/* missing: program for automatic rcomp evaluation cycles */
-
-	/* 5. DDR DRAM strobe delay calibration */
-	ldr		r0, =DDR_HCAL
-	ldr		r1, =0x88000007
-	str		r1, [r0]
-	wait		#5
-	ldr		r1, [r0]	/* delay until written */
-
-	/* Set MDMRS */
-	ldr		r0, =MDMRS
-	ldr		r1, =0x60000033
-	str		r1, [r0]
-	wait	#300
-
-	/* Configure MDREFR */
-	ldr		r0, =MDREFR
-	ldr		r1, =0x00000006
-	str		r1, [r0]
-	ldr		r1, [r0]
-
-	/* Enable the dynamic memory controller */
-	ldr		r0, =MDCNFG
-	ldr		r1, [r0]
-	orr		r1, r1, #MDCNFG_DMCEN
-	str		r1, [r0]
-
-#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
-	/* scrub/init SDRAM if enabled/present */
-	ldr	r8, =CONFIG_SYS_DRAM_BASE	/* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
-	ldr	r9, =CONFIG_SYS_DRAM_SIZE	/* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
-	mov	r0, #0			/* scrub with 0x0000:0000 */
-	mov	r1, #0
-	mov	r2, #0
-	mov	r3, #0
-	mov	r4, #0
-	mov	r5, #0
-	mov	r6, #0
-	mov	r7, #0
-10:	/* fastScrubLoop */
-	subs	r9, r9, #32	/* 8 words/line */
-	stmia	r8!, {r0-r7}
-	beq	15f
-	b	10b
-#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
-
-15:
-	/* Mask all interrupts */
-	mov	r1, #0
-	mcr	p6, 0, r1, c1, c0, 0	@ ICMR
-
-	/* Disable software and data breakpoints */
-	mov	r0, #0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/* Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-endlowlevel_init:
-	mov	pc, lr
diff --git a/board/delta/nand.c b/board/delta/nand.c
deleted file mode 100644
index 119a587..0000000
--- a/board/delta/nand.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_SYS_DFC_DEBUG1
-# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG1(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG2
-# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG2(fmt, args...)
-#endif
-
-#ifdef CONFIG_SYS_DFC_DEBUG3
-# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
-#else
-# define DFC_DEBUG3(fmt, args...)
-#endif
-
-/* These really don't belong here, as they are specific to the NAND Model */
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr delta_bbt_descr = {
-	.options = 0,
-	.offs = 0,
-	.len = 2,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout delta_oob = {
-	.eccbytes = 6,
-	.eccpos = {2, 3, 4, 5, 6, 7},
-	.oobfree = { {8, 2}, {12, 4} }
-};
-
-/*
- * not required for Monahans DFC
- */
-static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	return;
-}
-
-#if 0
-/* read device ready pin */
-static int dfc_device_ready(struct mtd_info *mtdinfo)
-{
-	if(NDSR & NDSR_RDY)
-		return 1;
-	else
-		return 0;
-	return 0;
-}
-#endif
-
-/*
- * Write buf to the DFC Controller Data Buffer
- */
-static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
-	unsigned long bytes_multi = len & 0xfffffffc;
-	unsigned long rest = len & 0x3;
-	unsigned long *long_buf;
-	int i;
-
-	DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
-	if(bytes_multi) {
-		for(i=0; i<bytes_multi; i+=4) {
-			long_buf = (unsigned long*) &buf[i];
-			writel(*long_buf, NDDB);
-		}
-	}
-	if(rest) {
-		printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
-	}
-	return;
-}
-
-
-static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
-{
-	int i=0, j;
-
-	/* we have to be carefull not to overflow the buffer if len is
-	 * not a multiple of 4 */
-	unsigned long bytes_multi = len & 0xfffffffc;
-	unsigned long rest = len & 0x3;
-	unsigned long *long_buf;
-
-	DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
-	/* if there are any, first copy multiple of 4 bytes */
-	if(bytes_multi) {
-		for(i=0; i<bytes_multi; i+=4) {
-			long_buf = (unsigned long*) &buf[i];
-			*long_buf = readl(NDDB);
-		}
-	}
-
-	/* ...then the rest */
-	if(rest) {
-		unsigned long rest_data = NDDB;
-		for(j=0;j<rest; j++)
-			buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
-	}
-
-	return;
-}
-
-/*
- * read a word. Not implemented as not used in NAND code.
- */
-static u16 dfc_read_word(struct mtd_info *mtd)
-{
-	printf("dfc_read_word: UNIMPLEMENTED.\n");
-	return 0;
-}
-
-/* global var, too bad: mk@tbd: move to ->priv pointer */
-static unsigned long read_buf = 0;
-static int bytes_read = -1;
-
-/*
- * read a byte from NDDB Because we can only read 4 bytes from NDDB at
- * a time, we buffer the remaining bytes. The buffer is reset when a
- * new command is sent to the chip.
- *
- * WARNING:
- * This function is currently only used to read status and id
- * bytes. For these commands always 8 bytes need to be read from
- * NDDB. So we read and discard these bytes right now. In case this
- * function is used for anything else in the future, we must check
- * what was the last command issued and read the appropriate amount of
- * bytes respectively.
- */
-static u_char dfc_read_byte(struct mtd_info *mtd)
-{
-	unsigned char byte;
-	unsigned long dummy;
-
-	if(bytes_read < 0) {
-		read_buf = readl(NDDB);
-		dummy = readl(NDDB);
-		bytes_read = 0;
-	}
-	byte = (unsigned char) (read_buf>>(8 * bytes_read++));
-	if(bytes_read >= 4)
-		bytes_read = -1;
-
-	DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
-	return byte;
-}
-
-/* calculate delta between OSCR values start and now  */
-static unsigned long get_delta(unsigned long start)
-{
-	unsigned long cur = readl(OSCR);
-
-	if(cur < start) /* OSCR overflowed */
-		return (cur + (start^0xffffffff));
-	else
-		return (cur - start);
-}
-
-/* delay function, this doesn't belong here */
-static void wait_us(unsigned long us)
-{
-	unsigned long start = readl(OSCR);
-	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
-
-	while (get_delta(start) < us) {
-		/* do nothing */
-	}
-}
-
-static void dfc_clear_nddb(void)
-{
-	writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
-	wait_us(CONFIG_SYS_NAND_OTHER_TO);
-}
-
-/* wait_event with timeout */
-static unsigned long dfc_wait_event(unsigned long event)
-{
-	unsigned long ndsr, timeout, start = readl(OSCR);
-
-	if(!event)
-		return 0xff000000;
-	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
-					* OSCR_CLK_FREQ, 1000);
-	else
-		timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
-					* OSCR_CLK_FREQ, 1000);
-
-	while(1) {
-		ndsr = readl(NDSR);
-		if(ndsr & event) {
-			writel(readl(NDSR) | event, NDSR);
-			break;
-		}
-		if(get_delta(start) > timeout) {
-			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
-			return 0xff000000;
-		}
-
-	}
-	return ndsr;
-}
-
-/* we don't always wan't to do this */
-static void dfc_new_cmd(void)
-{
-	int retry = 0;
-	unsigned long status;
-
-	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
-		/* Clear NDSR */
-		writel(0xfff, NDSR);
-
-		/* set NDCR[NDRUN] */
-		if (!(readl(NDCR) & NDCR_ND_RUN))
-			writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
-
-		status = dfc_wait_event(NDSR_WRCMDREQ);
-
-		if(status & NDSR_WRCMDREQ)
-			return;
-
-		DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
-		dfc_clear_nddb();
-	}
-	DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
-}
-
-/* this function is called after Programm and Erase Operations to
- * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
-{
-	unsigned long ndsr=0, event=0;
-	int state = this->state;
-
-	if(state == FL_WRITING) {
-		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
-	} else if(state == FL_ERASING) {
-		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
-	}
-
-	ndsr = dfc_wait_event(event);
-
-	if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
-		return(0x1); /* Status Read error */
-	return 0;
-}
-
-/* cmdfunc send commands to the DFC */
-static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
-			int column, int page_addr)
-{
-	/* register struct nand_chip *this = mtd->priv; */
-	unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
-
-	/* clear the ugly byte read buffer */
-	bytes_read = -1;
-	read_buf = 0;
-
-	switch (command) {
-	case NAND_CMD_READ0:
-		DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		dfc_new_cmd();
-		ndcb0 = (NAND_CMD_READ0 | (4<<16));
-		column >>= 1; /* adjust for 16 bit bus */
-		ndcb1 = (((column>>1) & 0xff) |
-			 ((page_addr<<8) & 0xff00) |
-			 ((page_addr<<8) & 0xff0000) |
-			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_READ1:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
-		goto end;
-	case NAND_CMD_READOOB:
-		DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
-		goto end;
-	case NAND_CMD_READID:
-		dfc_new_cmd();
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
-		ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_PAGEPROG:
-		/* sent as a multicommand in NAND_CMD_SEQIN */
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
-		goto end;
-	case NAND_CMD_ERASE1:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		dfc_new_cmd();
-		ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
-		ndcb1 = (page_addr & 0x00ffffff);
-		goto write_cmd;
-	case NAND_CMD_ERASE2:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
-		goto end;
-	case NAND_CMD_SEQIN:
-		/* send PAGE_PROG command(0x1080) */
-		dfc_new_cmd();
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG,  page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
-		ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
-		column >>= 1; /* adjust for 16 bit bus */
-		ndcb1 = (((column>>1) & 0xff) |
-			 ((page_addr<<8) & 0xff00) |
-			 ((page_addr<<8) & 0xff0000) |
-			 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
-		event = NDSR_WRDREQ;
-		goto write_cmd;
-	case NAND_CMD_STATUS:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
-		dfc_new_cmd();
-		ndcb0 = NAND_CMD_STATUS | (4<<21);
-		event = NDSR_RDDREQ;
-		goto write_cmd;
-	case NAND_CMD_RESET:
-		DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
-		ndcb0 = NAND_CMD_RESET | (5<<21);
-		event = NDSR_CS0_CMDD;
-		goto write_cmd;
-	default:
-		printk("dfc_cmdfunc: error, unsupported command.\n");
-		goto end;
-	}
-
- write_cmd:
-	writel(ndcb0, NDCB0);
-	writel(ndcb1, NDCB0);
-	writel(ndcb2, NDCB0);
-
-	/*  wait_event: */
-	dfc_wait_event(event);
- end:
-	return;
-}
-
-static void dfc_gpio_init(void)
-{
-	DFC_DEBUG2("Setting up DFC GPIO's.\n");
-
-	/* no idea what is done here, see zylonite.c */
-	writel(0x1, GPIO4);
-
-	writel(0x00000001, DF_ALE_nWE1);
-	writel(0x00000001, DF_ALE_nWE2);
-	writel(0x00000001, DF_nCS0);
-	writel(0x00000001, DF_nCS1);
-	writel(0x00000001, DF_nWE);
-	writel(0x00000001, DF_nRE);
-	writel(0x00000001, DF_IO0);
-	writel(0x00000001, DF_IO8);
-	writel(0x00000001, DF_IO1);
-	writel(0x00000001, DF_IO9);
-	writel(0x00000001, DF_IO2);
-	writel(0x00000001, DF_IO10);
-	writel(0x00000001, DF_IO3);
-	writel(0x00000001, DF_IO11);
-	writel(0x00000001, DF_IO4);
-	writel(0x00000001, DF_IO12);
-	writel(0x00000001, DF_IO5);
-	writel(0x00000001, DF_IO13);
-	writel(0x00000001, DF_IO6);
-	writel(0x00000001, DF_IO14);
-	writel(0x00000001, DF_IO7);
-	writel(0x00000001, DF_IO15);
-
-	writel(0x1901, DF_nWE);
-	writel(0x1901, DF_nRE);
-	writel(0x1900, DF_CLE_nOE);
-	writel(0x1901, DF_ALE_nWE1);
-	writel(0x1900, DF_INT_RnB);
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand_new.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for  accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
- *   only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
- * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
-
-	/* set up GPIO Control Registers */
-	dfc_gpio_init();
-
-	/* turn on the NAND Controller Clock (104 MHz @ D0) */
-	writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
-
-#undef CONFIG_SYS_TIMING_TIGHT
-#ifndef CONFIG_SYS_TIMING_TIGHT
-	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tCH);
-	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tCS);
-	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tWH);
-	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tWP);
-	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tRH);
-	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tRP);
-	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
-		 DFC_MAX_tR);
-	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
-		   DFC_MAX_tWHR);
-	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
-		  DFC_MAX_tAR);
-#else /* this is the tight timing */
-
-	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
-		  DFC_MAX_tCH);
-	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
-		  DFC_MAX_tCS);
-	tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
-		  DFC_MAX_tWH);
-	tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
-		  DFC_MAX_tWP);
-	tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
-		  DFC_MAX_tRH);
-	tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
-		  DFC_MAX_tRP);
-	tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
-		 DFC_MAX_tR);
-	tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
-		   DFC_MAX_tWHR);
-	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
-		  DFC_MAX_tAR);
-#endif /* CONFIG_SYS_TIMING_TIGHT */
-
-
-	DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
-
-	/* tRP value is split in the register */
-	if(tRP & (1 << 4)) {
-		tRP_high = 1;
-		tRP &= ~(1 << 4);
-	} else {
-		tRP_high = 0;
-	}
-
-	writel((tCH << 19) |
-		(tCS << 16) |
-		(tWH << 11) |
-		(tWP << 8) |
-		(tRP_high << 6) |
-		(tRH << 3) |
-		(tRP << 0),
-		NDTR0CS0);
-
-	writel((tR << 16) |
-		(tWHR << 4) |
-		(tAR << 0),
-		NDTR1CS0);
-
-	/* If it doesn't work (unlikely) think about:
-	 *  - ecc enable
-	 *  - chip select don't care
-	 *  - read id byte count
-	 *
-	 * Intentionally enabled by not setting bits:
-	 *  - dma (DMA_EN)
-	 *  - page size = 512
-	 *  - cs don't care, see if we can enable later!
-	 *  - row address start position (after second cycle)
-	 *  - pages per block = 32
-	 *  - ND_RDY : clears command buffer
-	 */
-	/* NDCR_NCSX |		/\* Chip select busy don't care *\/ */
-
-	writel(NDCR_SPARE_EN |		/* use the spare area */
-		NDCR_DWIDTH_C |		/* 16bit DFC data bus width  */
-		NDCR_DWIDTH_M |		/* 16 bit Flash device data bus width */
-		(2 << 16) |		/* read id count = 7 ???? mk@tbd */
-		NDCR_ND_ARB_EN |	/* enable bus arbiter */
-		NDCR_RDYM |		/* flash device ready ir masked */
-		NDCR_CS0_PAGEDM |	/* ND_nCSx page done ir masked */
-		NDCR_CS1_PAGEDM |
-		NDCR_CS0_CMDDM |	/* ND_CSx command done ir masked */
-		NDCR_CS1_CMDDM |
-		NDCR_CS0_BBDM |		/* ND_CSx bad block detect ir masked */
-		NDCR_CS1_BBDM |
-		NDCR_DBERRM |		/* double bit error ir masked */
-		NDCR_SBERRM |		/* single bit error ir masked */
-		NDCR_WRDREQM |		/* write data request ir masked */
-		NDCR_RDDREQM |		/* read data request ir masked */
-		NDCR_WRCMDREQM,		/* write command request ir masked */
-		NDCR);
-
-
-	/* wait 10 us due to cmd buffer clear reset */
-	/*	wait(10); */
-
-
-	nand->cmd_ctrl = dfc_hwcontrol;
-/*	nand->dev_ready = dfc_device_ready; */
-	nand->ecc.mode = NAND_ECC_SOFT;
-	nand->ecc.layout = &delta_oob;
-	nand->options = NAND_BUSWIDTH_16;
-	nand->waitfunc = dfc_wait;
-	nand->read_byte = dfc_read_byte;
-	nand->read_word = dfc_read_word;
-	nand->read_buf = dfc_read_buf;
-	nand->write_buf = dfc_write_buf;
-
-	nand->cmdfunc = dfc_cmdfunc;
-	nand->badblock_pattern = &delta_bbt_descr;
-	return 0;
-}
-
-#endif
diff --git a/board/innokom/Makefile b/board/innokom/Makefile
index afae217..ba248c0 100644
--- a/board/innokom/Makefile
+++ b/board/innokom/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= innokom.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/innokom/config.mk b/board/innokom/config.mk
deleted file mode 100644
index 9e46555..0000000
--- a/board/innokom/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Linux-Kernel is expected to be at c000'8000, entry c000'8000
-#
-# we load ourself to c170'0000, the upper 1 MB of second bank
-#
-# download areas is c800'0000
-#
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index 2c51125..e658c35 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -100,8 +100,9 @@ int misc_init_r(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
 	gd->bd->bi_boot_params = 0xa0000100;
@@ -110,22 +111,20 @@ int board_init (void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-/**
- * dram_init: - setup dynamic RAM
- *
- * @return: 0 in case of success
- */
-
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
-
 /**
  * innokom_set_led: - switch LEDs on or off
  *
diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S
deleted file mode 100644
index 55169be..0000000
--- a/board/innokom/lowlevel_init.S
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
-/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
-/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
-/* */
-/*	ldr	r1,	=LED_BLANK */
-/*	mov	r0,	#0xFF */
-/*	str	r0,	[r1]		/  turn on hex leds */
-/* */
-/*loop: */
-/* */
-/*   ldr	r0, =0xB0070001 */
-/*   ldr	r1, =_LED */
-/*   str	r0, [r1]		/  hex display */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
-	adr	r3, mem_init		/* r0 <- current position of code   */
-	ldr	r2, =mem_init
-	cmp	r3, r2			/* skip init if in place            */
-	beq	initirqs
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	ldr	r2,	=0xFFF
-	and	r3,	r3, r2
-	ldr	r4,	=0x03ca4000
-	orr	r4,	r4,  r3
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,	[r1, #MDREFR_OFFSET]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* Step 4a: assert MDREFR:K?RUN and configure                       */
-	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
-
-	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4, #(MDREFR_SLFRSH)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
-
-	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	/*          There should 9 writes, since the first write doesn't    */
-	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
-	/*          PXA210 Processors Specification Update,                 */
-	/*          Jan 2003, Errata #116, page 30.                         */
-
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-	str	r2, [r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr	r3, [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str	r3, [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-/*
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-*/
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size                                                  */
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR			/* enable no sources        */
-	mov	r1, #0
-	str	r1, [r0]
-
-	/* FIXME */
-
-#ifndef DEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr
diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile
index 6592307..2853bca 100644
--- a/board/lubbock/Makefile
+++ b/board/lubbock/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= lubbock.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/lubbock/config.mk b/board/lubbock/config.mk
deleted file mode 100644
index f30f695..0000000
--- a/board/lubbock/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S
deleted file mode 100644
index db6f69d..0000000
--- a/board/lubbock/lowlevel_init.S
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc  p15,0,\reg,c2,c0,0
-   mov  \reg,\reg
-   sub  pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-    mov      r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
-	ldr     r2,     =0xFFF
-	and     r3,     r3,  r2
-	ldr	r4,	=0x03ca4000
-	orr     r4,     r4,  r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4                            */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	orr	r4,	r4,	#(MDREFR_SLFRSH)
-	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4,	#(MDREFR_SLFRSH)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	    str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-    ldr     r1, =DRAM_SIZE
-	 str	   r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-    ldr	r0, =ICMR /* enable no sources */
-	mov r1, #0
-    str r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-    mov     pc, lr
diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c
index d8d6ffb..f791c5b 100644
--- a/board/lubbock/lubbock.c
+++ b/board/lubbock/lubbock.c
@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
@@ -55,19 +56,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
index bcb014d..0cca8ab 100644
--- a/board/palmld/Makefile
+++ b/board/palmld/Makefile
@@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= palmld.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmld/config.mk b/board/palmld/config.mk
deleted file mode 100644
index 1d650ac..0000000
--- a/board/palmld/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000
diff --git a/board/palmld/lowlevel_init.S b/board/palmld/lowlevel_init.S
deleted file mode 100644
index e3382ee..0000000
--- a/board/palmld/lowlevel_init.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Palm LifeDrive Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-
-	/* Enable GPIO reset */
-	ldr	r0, =PCFR
-	mov	r1, #0x30
-	str	r1, [r0]
-
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
index 4f0087e..5588fe7 100644
--- a/board/palmld/palmld.c
+++ b/board/palmld/palmld.c
@@ -33,7 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	/* arch number of Lubbock-Board */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* arch number of PalmLD */
 	gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
 
 	/* adress of boot parameters */
@@ -52,12 +56,18 @@ struct serial_device *default_serial_console(void)
 	return &serial_ffuart_device;
 }
 
+extern void pxa_dram_init(void);
 int dram_init(void)
 {
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
 }
 
 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
diff --git a/board/palmld/u-boot.lds b/board/palmld/u-boot.lds
deleted file mode 100644
index fb4358b..0000000
--- a/board/palmld/u-boot.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  cpu/pxa/start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
index 20ac4e1..3a12e66 100644
--- a/board/palmtc/Makefile
+++ b/board/palmtc/Makefile
@@ -24,17 +24,16 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= palmtc.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/palmtc/config.mk b/board/palmtc/config.mk
deleted file mode 100644
index 1d650ac..0000000
--- a/board/palmtc/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-TEXT_BASE = 0xa1000000
diff --git a/board/palmtc/lowlevel_init.S b/board/palmtc/lowlevel_init.S
deleted file mode 100644
index 74050dc..0000000
--- a/board/palmtc/lowlevel_init.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Palm Tungsten|C Lowlevel Hardware Initialization
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	pxa_gpio_setup
-	pxa_wait_ticks	0x8000
-	pxa_mem_setup
-	pxa_wakeup
-	pxa_intr_setup
-	pxa_clock_setup
-
-	mov	pc, lr
diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c
index 04cb33e..25186ae 100644
--- a/board/palmtc/palmtc.c
+++ b/board/palmtc/palmtc.c
@@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	/* Arch number of Palm Tungsten|C */
 	gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
 
@@ -51,9 +55,16 @@ struct serial_device *default_serial_console(void)
 	return &serial_ffuart_device;
 }
 
+extern void pxa_dram_init(void);
 int dram_init(void)
 {
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	return 0;
 }
diff --git a/board/palmtc/u-boot.lds b/board/palmtc/u-boot.lds
deleted file mode 100644
index fb4358b..0000000
--- a/board/palmtc/u-boot.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	  cpu/pxa/start.o	(.text)
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
-	_end = .;
-}
diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile
index faa2691..cb0c3d7 100644
--- a/board/pleb2/Makefile
+++ b/board/pleb2/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= pleb2.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/pleb2/config.mk b/board/pleb2/config.mk
deleted file mode 100644
index 079f58e..0000000
--- a/board/pleb2/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE =  0xa1F80000
-#CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S
deleted file mode 100644
index b95ff9c..0000000
--- a/board/pleb2/lowlevel_init.S
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc	p15,0,\reg,c2,c0,0
-	mov	\reg,\reg
-	sub	pc,pc,#4
-	.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-	/* Set up GPIO pins first */
-
-	ldr	r0,   =GPSR0
-	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR1
-	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR2
-	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR0
-	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR1
-	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR2
-	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER0
-	ldr	r1,   =CONFIG_SYS_GRER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER1
-	ldr	r1,   =CONFIG_SYS_GRER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER2
-	ldr	r1,   =CONFIG_SYS_GRER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER0
-	ldr	r1,   =CONFIG_SYS_GFER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER1
-	ldr	r1,   =CONFIG_SYS_GFER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER2
-	ldr	r1,   =CONFIG_SYS_GFER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR0
-	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR1
-	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR2
-	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_L
-	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_U
-	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_L
-	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_U
-	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_L
-	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_U
-	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
-	str	r1,   [r0]
-
-	/* enable GPIO pins */
-	ldr	r0,   =PSSR
-	ldr	r1,   =CONFIG_SYS_PSSR_VAL
-	str	r1,   [r0]
-
-
-/*********************************************************************
-    Initlialize Memory Controller
-
-    See PXA250 Operating System Developer's Guide
-
-    pause for 200 uSecs- allow internal clocks to settle
-    *Note: only need this if hard reset... doing it anyway for now
-*/
-
-	@ Step 1
-	@ ---- Wait 200 usec
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-	@ get memory controller base address
-	ldr	r1,  =MEMC_BASE
-
-@****************************************************************************
-@  Step 2
-@
-
-	@ Step 2a
-	@ write msc0, read back to ensure data latches
-	@
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]
-
-	@ write msc1
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	@ write msc2
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-
-@ Step 2b
-	@ write mecr
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-
-	@ write mcmem0
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-
-	@ write mcmem1
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-
-	@ write mcatt0
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-
-	@ write mcatt1
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-
-	@ write mcio0
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-
-	@ write mcio1
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-
-@ Step 2c
-	@ fly-by-dma is defeatured on this part
-	@ write flycnfg
-	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	@str	r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ extract DRI field (we need a valid DRI field)
-	@
-	ldr	r2,  =0xFFF
-
-	@ valid DRI field in r3
-	@
-	and	r3,  r3,  r2
-
-	@ get the reset state of MDREFR
-	@
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ clear the DRI field
-	@
-	bic	r4,  r4,  r2
-
-	@ insert the valid DRI field loaded above
-	@
-	orr	r4,  r4,  r3
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ *Note: preserve the mdrefr value in r4 *
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-	mov	pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-	@ clear the free-running clock bits
-	@ (clear K0Free, K1Free, K2Free
-	@
-	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4,  #0x00002000
-
-	@ set K1RUN if bank 0 installed
-	@
-	orr	r4,  r4,  #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#else
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@  Step 4
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4,  #0x00002000
-
-	@ set K1RUN for bank 0
-	@
-	orr	r4,  r4,  #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#endif
-
-	@ Step 4d
-	@ fetch platform value of mdcnfg
-	@
-	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic	r2,  r2,  #MDCNFG_DWID0	     @0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str	r2,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4e
-	@ pause for 200 uSecs
-	@
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-	1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-	/* Why is this here??? */
-	mov	r0, #0x78		 @turn everything off
-	mcr	p15, 0, r0, c1, c0, 0	   @(caches off, MMU off, etc.)
-
-	@ Step 4f
-	@ Access memory *not yet enabled* for CBR refresh cycles (8)
-	@ - CBR is generated for all banks
-
-	ldr	r2, =CONFIG_SYS_DRAM_BASE
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-
-	@ Step 4g
-	@get memory controller base address
-	@
-	ldr	r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr	r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr	r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str	r3,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4h
-	@ write mdmrs
-	@
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	@ Done Memory Init
-
-	/*SET_LED 6 */
-
-	@********************************************************************
-	@ Disable (mask) all interrupts at the interrupt controller
-	@
-
-	@ clear the interrupt level register (use IRQ, not FIQ)
-	@
-	mov	r1, #0
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	@ Set interrupt mask register
-	@
-	ldr	r1,  =CONFIG_SYS_ICMR_VAL
-	ldr	r2,  =ICMR
-	str	r1,  [r2]
-
-	@ ********************************************************************
-	@ Disable the peripheral clocks, and set the core clock
-	@
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-	ldr	r1,  =CKEN
-	mov	r2,  #0
-	str	r2,  [r1]
-
-	@ set core clocks
-	@
-	ldr	r2,  =CONFIG_SYS_CCCR_VAL
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-	#ifdef ENABLE32KHZ
-	@ enable the 32Khz oscillator for RTC and PowerManager
-	@
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	@ NOTE:	 spin here until OSCC.OOK get set,
-	@	 meaning the PLL has settled.
-	@
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#endif
-
-	@ Turn on needed clocks
-	@
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN_VAL
-	str	r2,  [r1]
-
-	/*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-   /*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	mov	pc, r10
-
-@ End lowlevel_init
diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c
index 97c37ea..5a16cc7 100644
--- a/board/pleb2/pleb2.c
+++ b/board/pleb2/pleb2.c
@@ -36,8 +36,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
@@ -55,17 +56,16 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
index 4892b42..2835f37 100644
--- a/board/pxa255_idp/Makefile
+++ b/board/pxa255_idp/Makefile
@@ -27,17 +27,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= pxa_idp.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk
deleted file mode 100644
index f30f695..0000000
--- a/board/pxa255_idp/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-#CONFIG_SYS_TEXT_BASE = 0xa1700000
-CONFIG_SYS_TEXT_BASE = 0xa3080000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S
deleted file mode 100644
index a50760f..0000000
--- a/board/pxa255_idp/lowlevel_init.S
+++ /dev/null
@@ -1,496 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-/*
- *	Memory setup
- */
-.globl lowlevel_init
-lowlevel_init:
-
-	mov      r10, lr
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 3rd blink */
-	bl	blink
-#endif
-
-	/* Set up GPIO pins first ----------------------------------------- */
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 4th debug blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CONFIG_SYS_MSC0_VAL
-	str     r2,   [r1, #MSC0_OFFSET]
-	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
-						/* that data latches        */
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC1_VAL
-	str     r2,  [r1, #MSC1_OFFSET]
-	ldr     r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CONFIG_SYS_MSC2_VAL
-	str     r2,  [r1, #MSC2_OFFSET]
-	ldr     r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CONFIG_SYS_MECR_VAL
-	str     r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
-	str     r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
-	str     r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
-	str     r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
-	str     r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
-	str     r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
-	str     r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 5th blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set     */
-	/* this to power on defaults + DRI field.                           */
-
-	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
-	ldr     r2,     =0xFFF
-	and     r3,     r3,  r2
-	ldr	r4,	=0x03ca4000
-	orr     r4,     r4,  r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4                            */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	/* set MDREFR according to user define with exception of a few bits */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	orr	r4,	r4,	#(MDREFR_SLFRSH)
-	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
-
-	bic	r4,	r4,	#(MDREFR_SLFRSH)
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
-
-	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
-	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
-	ldr     r4,     [r1, #MDREFR_OFFSET]
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*          configure but not enable each SDRAM partition pair.     */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-
-	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
-	ldr     r4,     [r1, #MDCNFG_OFFSET]
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	    str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/*          (MDCNFG:DEx set to 1).                                  */
-
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-	str     r2,  [r1, #MDMRS_OFFSET]
-
-	/* We are finished with Intel's memory controller initialisation    */
-#if 0
-	/* FIXME turn on serial ports */
-	/* look into moving this to board_init() */
-	ldr	r2, =(PXA_CS5_PHYS + 0x03C0002c)
-	mov	r3, #0x13
-	str	r3, [r2]
-#endif
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 6th blink */
-	bl	blink
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
-	str     r1,  [r2]
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-#if 0
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-	/* default value in case no valid rotary switch setting is found    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#endif
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size */
-	ldr     r1, =DRAM_SIZE
-	str     r8, [r1]
-
-	/* Interrupt init: Mask all interrupts                              */
-	ldr	r0, =ICMR /* enable no sources */
-	mov r1, #0
-	str r1, [r0]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
-	/* ---------------------------------------------------------------- */
-
-#ifdef DEBUG_BLINK_ENABLE
-	/* 7th blink */
-	bl	blink
-#endif
-
-endlowlevel_init:
-
-	mov     pc, r10
-
-
-#ifdef DEBUG_BLINK_ENABLE
-
-/* debug LED code */
-
-/* delay about 200ms */
-delay:
-
-	/* reset OSCR to 0 */
-	ldr	r8, =OSCR
-	mov	r9, #0
-	str	r9, [r8]
-
-	/* make sure new value has stuck */
-1:
-	ldr	r8, =OSCR
-	ldr	r9, [r8]
-	mov	r8, #0x10000
-	cmp	r9, r8
-	bgt	1b
-
-	/* now, wait for delay to expire */
-1:
-	ldr	r8, =OSCR
-	ldr	r9, [r8]
-	mov	r8, #0xd4000
-	cmp	r8, r9
-	bgt	1b
-
-	mov	pc, lr
-
-/* blink code -- trashes r7, r8, r9 */
-
-.globl blink
-blink:
-
-	mov	r7, lr
-
-	/* set GPIO10 as outout */
-	ldr	r8,  =GPDR0
-	ldr	r9,  [r8]
-	orr	r9,  r9, #(1<<10)
-	str	r9,  [r8]
-
-	/* turn LED off */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPCR0
-	str	r9, [r8]
-	bl	delay
-
-	/* turn LED on */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPSR0
-	str	r9, [r8]
-	bl	delay
-
-	/* turn LED off */
-	mov	r9,  #(1<<10)
-	ldr	r8,  =GPCR0
-	str	r9, [r8]
-
-	mov	pc, r7
-
-#endif
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index 4ab8bd4..804d09c 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -43,8 +43,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of Lubbock-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
@@ -82,22 +83,20 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
-
 #ifdef DEBUG_BLINKC_ENABLE
 
 void delay_c(void)
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
index 44c0d49..060ac89 100644
--- a/board/trizepsiv/Makefile
+++ b/board/trizepsiv/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= conxs.o eeprom.o
-SOBJS	:= lowlevel_init.o pxavoltage.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk
deleted file mode 100644
index f04eb74..0000000
--- a/board/trizepsiv/config.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_SYS_TEXT_BASE =0xa1f00000
-# 0xa1700000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 0c67367..99f665b 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -104,8 +104,9 @@ void usb_board_stop(void)
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of ConXS Board */
 	gd->bd->bi_arch_number = 776;
@@ -138,18 +139,18 @@ struct serial_device *default_serial_console (void)
 	return &serial_ffuart_device;
 }
 
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
-	return 0;
 }
 
 #ifdef CONFIG_DRIVER_DM9000
diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S
deleted file mode 100644
index 128d554..0000000
--- a/board/trizepsiv/lowlevel_init.S
+++ /dev/null
@@ -1,503 +0,0 @@
-/*
- * This was originally from the Lubbock u-boot port.
- *
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* wait for coprocessor write complete */
-   .macro CPWAIT reg
-   mrc	p15,0,\reg,c2,c0,0
-   mov	\reg,\reg
-   sub	pc,pc,#4
-   .endm
-
-
-/*
- *	Memory setup
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr		r0,	=GPSR0
-	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR1
-	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR2
-	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPSR3
-	ldr		r1,	=CONFIG_SYS_GPSR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR0
-	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR1
-	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR2
-	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPCR3
-	ldr		r1,	=CONFIG_SYS_GPCR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER0
-	ldr		r1,	=CONFIG_SYS_GRER0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER1
-	ldr		r1,	=CONFIG_SYS_GRER1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER2
-	ldr		r1,	=CONFIG_SYS_GRER2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GRER3
-	ldr		r1,	=CONFIG_SYS_GRER3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER0
-	ldr		r1,	=CONFIG_SYS_GFER0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER1
-	ldr		r1,	=CONFIG_SYS_GFER1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER2
-	ldr		r1,	=CONFIG_SYS_GFER2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GFER3
-	ldr		r1,	=CONFIG_SYS_GFER3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR0
-	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR1
-	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR2
-	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GPDR3
-	ldr		r1,	=CONFIG_SYS_GPDR3_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR3_L
-	ldr		r1,	=CONFIG_SYS_GAFR3_L_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=GAFR3_U
-	ldr		r1,	=CONFIG_SYS_GAFR3_U_VAL
-	str		r1,   [r0]
-
-	ldr		r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CONFIG_SYS_PSSR_VAL
-	str		r1,   [r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface					    */
-	/*								    */
-	/* The sequence below is based on the recommended init steps	    */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.							    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
-	/*	   clocks to settle. Only necessary after hard reset...	    */
-	/*	   FIXME: can be optimized later			    */
-	/* ---------------------------------------------------------------- */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty	    */
-1:
-	ldr r2, [r3]
-	cmp r4, r2
-	bgt 1b
-
-mem_init:
-
-	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller	    */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type			    */
-
-	/* MSC0: nCS(0,1)						    */
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
-						/* that data latches	    */
-	/* MSC1: nCS(2,3)						    */
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)						    */
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface				    */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register				    */
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-	ldr	r2,	[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing				    */
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-	ldr	r2,	[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing				    */
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-	ldr	r2,	[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-	ldr	r2,	[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-	ldr	r2,	[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-	ldr	r2,	[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-	ldr	r2,	[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
-	/* ---------------------------------------------------------------- */
-	ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	str	r2,  [r1, #FLYCNFG_OFFSET]
-	str	r2,	[r1, #FLYCNFG_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
-	/* ---------------------------------------------------------------- */
-
-	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
-	/* this to power on defaults + DRI field.			    */
-
-	ldr	r4,	[r1, #MDREFR_OFFSET]
-	ldr	r2,	=0xFFF
-	bic	r4,	r4, r2
-
-	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
-	and	r3,	r3,  r2
-
-	orr	r4,	r4, r3
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
-
-	orr	r4,  r4, #MDREFR_K0RUN
-	orr	r4,  r4, #MDREFR_K0DB4
-	orr	r4,  r4, #MDREFR_K0FREE
-	orr	r4,  r4, #MDREFR_K0DB2
-	orr	r4,  r4, #MDREFR_K1DB2
-	bic	r4,  r4, #MDREFR_K1FREE
-	bic	r4,  r4, #MDREFR_K2FREE
-
-	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	/* Note: preserve the mdrefr value in r4			    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits		    */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.						    */
-
-	ldr	r2,  =CONFIG_SYS_SXCNFG_VAL
-	str	r2,  [r1, #SXCNFG_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM					    */
-	/* ---------------------------------------------------------------- */
-
-	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
-
-	orr	r4, r4, #MDREFR_K1RUN
-	bic	r4, r4, #MDREFR_K2DB2
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	bic	r4, r4, #MDREFR_SLFRSH
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	orr	r4, r4, #MDREFR_E1PIN
-	str	r4, [r1, #MDREFR_OFFSET]
-	ldr	r4, [r1, #MDREFR_OFFSET]
-
-	nop
-	nop
-
-
-	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
-	/*	    configure but not enable each SDRAM partition pair.	    */
-
-	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
-	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
-	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
-
-	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
-	ldr	r4,	[r1, #MDCNFG_OFFSET]
-
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
-	/*	    100..200 µsec.					    */
-
-	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
-	mov r2, #0
-	str r2, [r3]
-	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty	    */
-1:
-	    ldr r2, [r3]
-	    cmp r4, r2
-	    bgt 1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
-	/*	    attempting non-burst read or write accesses to disabled */
-	/*	    SDRAM, as commonly specified in the power up sequence   */
-	/*	    documented in SDRAM data sheets. The address(es) used   */
-	/*	    for this purpose must not be cacheable.		    */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted		    */
-	/*	    (MDCNFG:DEx set to 1).				    */
-
-	ldr	r3,	[r1, #MDCNFG_OFFSET]
-	mov	r4, r3
-	orr	r3,	r3,	#MDCNFG_DE0
-	str	r3,	[r1, #MDCNFG_OFFSET]
-	mov	r0, r3
-
-	/* Step 4h: Write MDMRS.					    */
-
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	/* enable APD */
-	ldr	r3,  [r1, #MDREFR_OFFSET]
-	orr	r3,  r3,  #MDREFR_APD
-	str	r3,  [r1, #MDREFR_OFFSET]
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-setvoltage:
-
-	mov	r10,	lr
-	bl	initPXAvoltage	/* In case the board is rebooting with a    */
-	mov	lr,	r10	/* low voltage raise it up to a good one.   */
-
-#if 1
-	b initirqs
-#endif
-
-wakeup:
-	/* Are we waking from sleep? */
-	ldr	r0,	=RCSR
-	ldr	r1,	[r0]
-	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
-	str	r1,	[r0]
-	teq	r1,	#RCSR_SMR
-
-	bne	initirqs
-
-	ldr	r0,	=PSSR
-	mov	r1,	#PSSR_PH
-	str	r1,	[r0]
-
-	/* if so, resume at PSPR */
-	ldr	r0,	=PSPR
-	ldr	r1,	[r0]
-	mov	pc,	r1
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller	    */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-
-	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
-	str	r1,  [r2]
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation						    */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-
-	/* Turn Off on-chip peripheral clocks (except for memory)	    */
-	/* for re-configuration.					    */
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN
-	str	r2,  [r1]
-
-	/* ... and write the core clock config register			    */
-	ldr	r2,  =CONFIG_SYS_CCCR
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-	/* Turn on turbo mode */
-	mrc	p14, 0, r2, c6, c0, 0
-	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
-	mcr	p14, 0, r2, c6, c0, 0
-
-	/* Re-write MDREFR */
-	ldr	r1, =MEMC_BASE
-	ldr	r2, [r1, #MDREFR_OFFSET]
-	str	r2, [r1, #MDREFR_OFFSET]
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager		    */
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
-	/* has settled.							    */
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#else
-#error "RTC not defined"
-#endif
-
-	/* Interrupt init: Mask all interrupts				    */
-    ldr r0, =ICMR /* enable no sources */
-	mov r1, #0
-    str r1, [r0]
-	/* FIXME */
-
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init							    */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov	pc, lr
diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S
deleted file mode 100644
index 9659c2b..0000000
--- a/board/trizepsiv/pxavoltage.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefano Babic, DENX Gmbh, sbabic@denx.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/pxa-regs.h>
-
-		.global	initPXAvoltage
-
-initPXAvoltage:
-		mov	pc, lr
diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile
deleted file mode 100644
index 0669b0e..0000000
--- a/board/wepep250/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= wepep250.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk
deleted file mode 100644
index 60cbc24..0000000
--- a/board/wepep250/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# This is config used for compilation of WEP EP250 sources
-#
-# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE.
-# This allows for example having one copy located at the end of ram and stored
-# in flash device and later on while developing use other location to test
-# the code in RAM device only.
-#
-
-CONFIG_SYS_TEXT_BASE = 0xa1fe0000
-#CONFIG_SYS_TEXT_BASE = 0xa1001000
diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c
deleted file mode 100644
index c6e9171..0000000
--- a/board/wepep250/flash.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This code was inspired by Marius Groeger and Kyle Harris code
- * available in other board ports for U-Boot
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include "intel.h"
-
-
-/*
- * This code should handle CFI FLASH memory device. This code is very
- * minimalistic approach without many essential error handling code as well.
- * Because U-Boot actually is missing smart handling of FLASH device,
- * we just set flash_id to anything else to FLASH_UNKNOW, so common code
- * can call us without any restrictions.
- * TODO: Add CFI Query, to be able to determine FLASH device.
- * TODO: Add error handling code
- * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
- *       hopefully may work with other configurations.
- */
-
-#if ( WEP_FLASH_BUS_WIDTH == 1 )
-#  define FLASH_BUS vu_char
-#  define FLASH_BUS_RET u_char
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  else
-#    error "With 8bit bus only one chip is allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 2 )
-#  define FLASH_BUS vu_short
-#  define FLASH_BUS_RET u_short
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 8 )| x )
-#  else
-#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
-#  endif
-
-
-#elif ( WEP_FLASH_BUS_WIDTH == 4 )
-#  define FLASH_BUS vu_long
-#  define FLASH_BUS_RET u_long
-#  if ( WEP_FLASH_INTERLEAVE == 1 )
-#    define FLASH_CMD( x ) x
-#  elif ( WEP_FLASH_INTERLEAVE == 2 )
-#    define FLASH_CMD( x ) (( x << 16 )| x )
-#  elif ( WEP_FLASH_INTERLEAVE == 4 )
-#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
-#  else
-#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
-#  endif
-
-#else
-#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
-#endif
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-static FLASH_BUS_RET flash_status_reg (void)
-{
-
-	FLASH_BUS *addr = (FLASH_BUS *) 0;
-
-	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
-
-	return *addr;
-}
-
-static int flash_ready (ulong timeout)
-{
-	int ok = 1;
-
-	reset_timer_masked ();
-	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
-		   FLASH_CMD (CFI_INTEL_SR_READY)) {
-		if (get_timer_masked () > timeout && timeout != 0) {
-			ok = 0;
-			break;
-		}
-	}
-	return ok;
-}
-
-#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
-#  error "WEP platform has only one flash bank!"
-#endif
-
-
-ulong flash_init (void)
-{
-	int i;
-	FLASH_BUS address = WEP_FLASH_BASE;
-
-	flash_info[0].size = WEP_FLASH_BANK_SIZE;
-	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	flash_info[0].flash_id = INTEL_MANUFACT;
-	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
-		flash_info[0].start[i] = address;
-#ifdef WEP_FLASH_UNLOCK
-		/* Some devices are hw locked after start. */
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
-		flash_ready (0);
-		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-#endif
-		address += WEP_FLASH_SECT_SIZE;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_SYS_FLASH_BASE,
-				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-				   &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-				   CONFIG_ENV_ADDR,
-				   CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return WEP_FLASH_BANK_SIZE;
-}
-
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	printf (" Intel vendor\n");
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if (!(i % 5)) {
-			printf ("\n");
-		}
-
-		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-}
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, non_protected = 0, sector;
-	int rc = ERR_OK;
-
-	FLASH_BUS *address;
-
-	for (sector = s_first; sector <= s_last; sector++) {
-		if (!info->protect[sector]) {
-			non_protected++;
-		}
-	}
-
-	if (!non_protected) {
-		return ERR_PROTECTED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	flag = disable_interrupts ();
-
-
-	/* Start erase on unprotected sectors */
-	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
-		if (info->protect[sector]) {
-			printf ("Protected sector %2d skipping...\n", sector);
-			continue;
-		} else {
-			printf ("Erasing sector %2d ... ", sector);
-		}
-
-		address = (FLASH_BUS *) (info->start[sector]);
-
-		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
-		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
-		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
-			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-			printf ("ok.\n");
-		} else {
-			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-			rc = ERR_TIMOUT;
-			printf ("timeout! Aborting...\n");
-			break;
-		}
-		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	}
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
-{
-	FLASH_BUS *address = (FLASH_BUS *) dest;
-	int rc = ERR_OK;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*address & data) != data) {
-		return ERR_NOT_ERASED;
-	}
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-
-	flag = disable_interrupts ();
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
-	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
-	*address = data;
-
-	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
-		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
-		rc = ERR_TIMOUT;
-		printf ("timeout! Aborting...\n");
-	}
-
-	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
-	if (flag) {
-		enable_interrupts ();
-	}
-
-	return rc;
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong read_addr, write_addr;
-	FLASH_BUS data;
-	int i, result = ERR_OK;
-
-
-	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
-	write_addr = read_addr;
-	if (read_addr != addr) {
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (read_addr < addr || cnt == 0) {
-				data |= *((uchar *) read_addr) << i * 8;
-			} else {
-				data |= (*src++) << i * 8;
-				cnt--;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-	}
-	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
-		if ((result = write_data (info, write_addr,
-								  *((FLASH_BUS *) src))) != ERR_OK) {
-			return result;
-		}
-		write_addr += sizeof (FLASH_BUS);
-		src += sizeof (FLASH_BUS);
-	}
-	if (cnt > 0) {
-		read_addr = write_addr;
-		data = 0;
-		for (i = 0; i < sizeof (FLASH_BUS); i++) {
-			if (cnt > 0) {
-				data |= (*src++) << i * 8;
-				cnt--;
-			} else {
-				data |= *((uchar *) read_addr) << i * 8;
-			}
-			read_addr++;
-		}
-		if ((result = write_data (info, write_addr, data)) != 0) {
-			return result;
-		}
-	}
-	return ERR_OK;
-}
diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h
deleted file mode 100644
index 77498b6..0000000
--- a/board/wepep250/intel.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (C) 2002 ETC s.r.o.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2002.
- *
- * Documentation:
- * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
- *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
- * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
- *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- */
-
-#ifndef	FLASH_INTEL_H
-#define	FLASH_INTEL_H
-
-#include <common.h>
-
-/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
-
-#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
-
-#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
-#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
-
-/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
-
-#define	CFI_CHIP_INTEL_28F320J3A		0x0016
-#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
-#define	CFI_CHIP_INTEL_28F640J3A		0x0017
-#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
-#define	CFI_CHIP_INTEL_28F128J3A		0x0018
-#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
-
-/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
-
-#define	CFI_CHIP_INTEL_28F640K3			0x8801
-#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
-#define	CFI_CHIP_INTEL_28F128K3			0x8802
-#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
-#define	CFI_CHIP_INTEL_28F256K3			0x8803
-#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
-#define	CFI_CHIP_INTEL_28F640K18		0x8805
-#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
-#define	CFI_CHIP_INTEL_28F128K18		0x8806
-#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
-#define	CFI_CHIP_INTEL_28F256K18		0x8807
-#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
-
-#endif /* FLASH_INTEL_H */
diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S
deleted file mode 100644
index 9bb091f..0000000
--- a/board/wepep250/lowlevel_init.S
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2001, 2002 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
- * 02111-1307, USA.
- *
- * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
- * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
- *
- * This file is taken from OpenWinCE project hosted by SourceForge.net
- *
- * Documentation:
- * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
- *     Developer's Manual", February 2002, Order Number: 278522-001
- * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
- *     Revision 1.0, February 2002
- * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
- *     Revision 1.0, February 2002
- *
-*/
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-/*	setup memory - see 6.12 in [1]
- *	Step 1	- wait 200 us
- */
-	mov	r0,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r0, r0, #1
-	bne	1b
-/*	TODO: complete step 1 for Synchronous Static memory*/
-
-	ldr	r0, =0x48000000			/* MC_BASE */
-
-
-/*	step 1.a - setup MSCx
- */
-	ldr	r1, =0x000012B3			/* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
-	str	r1, [r0, #0x8]			/* MSC0_OFFSET */
-
-/*	step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
- *	see AUTO REFRESH chapter in section D. in [2] and in [3]
- *	DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
- *	DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
- *	TODO: complete for Synchronous Static memory
- */
-	ldr	r1, [r0, #4]			/* MDREFR_OFFSET */
-	ldr	r2, =0x01000FFF			/* MDREFR_K1FREE | MDREFR_DRI_MASK */
-	bic	r1, r1, r2
-#if defined( WEP_SDRAM_K4S281633 )
-	orr	r1, r1, #48			/* MDREFR_DRI(48) */
-#elif defined( WEP_SDRAM_K4S561633 )
-	orr	r1, r1, #24			/* MDREFR_DRI(24) */
-#else
-#error SDRAM chip is not defined
-#endif
-
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 2 - only for Synchronous Static memory (TODO)
- *
- *	Step 3 - same as step 4
- *
- *	Step 4
- *
- *	Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
- */
-	orr	r1, r1, #0x00010000		/* MDREFR_K1RUN */
-	bic	r1, r1, #0x00020000		/* MDREFR_K1DB2 */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.b - clear MDREFR:SLFRSH */
-	bic	r1, r1, #0x00400000		/* MDREFR_SLFRSH */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.c - set MDREFR:E1PIN */
-	orr	r1, r1, #0x00008000		/* MDREFR_E1PIN */
-	str	r1, [r0, #4]			/* MDREFR_OFFSET */
-
-/*	Step 4.d - automatically done
- *
- *	Steps 4.e and 4.f - configure SDRAM
- */
-#if defined( WEP_SDRAM_K4S281633 )
-	ldr	r1, =0x00000AA8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
-#elif defined( WEP_SDRAM_K4S561633 )
-	ldr	r1, =0x00000AC8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
-#else
-#error SDRAM chip is not defined
-#endif
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 5 - wait at least 200 us for SDRAM
- *	see section B. in [2]
- */
-	mov	r2,#0x2700			/* wait 200 us @ 99.5 MHz */
-1:	subs	r2, r2, #1
-	bne	1b
-
-/*	Step 6 - after reset dcache is disabled, so automatically done
- *
- *	Step 7 - eight refresh cycles
- */
-	mov	r2, #0xA0000000
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-	ldr	r3, [r2]
-
-/*	Step 8 - we don't need dcache now
- *
- *	Step 9 - enable SDRAM partition 0
- */
-	orr	r1, r1, #1			/* MDCNFG_DE0 */
-	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
-
-/*	Step 10 - write MDMRS */
-	mov	r1, #0
-	str	r1, [r0, #0x40]			/* MDMRS_OFFSET */
-
-/*	Step 11 - optional (TODO) */
-
-	mov	pc,r10
diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
deleted file mode 100644
index 6e41ea6..0000000
--- a/board/wepep250/wepep250.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init (void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
-	gd->bd->bi_boot_params = 0xa0000000;
-/*
- * Setup GPIO stuff to get serial working
- */
-#if defined( CONFIG_FFUART )
-	writel(0x80, GPDR1);
-	writel(0x8010, GAFR1_L);
-#elif defined( CONFIG_BTUART )
-	writel(0x800, GPDR1);
-	writel(0x900000, GAFR1_L);
-#endif
-	writel(0x20, PSSR);
-
-	return 0;
-}
-
-int dram_init (void)
-{
-#if ( CONFIG_NR_DRAM_BANKS > 0 )
-	gd->bd->bi_dram[0].start = WEP_SDRAM_1;
-	gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 1 )
-	gd->bd->bi_dram[1].start = WEP_SDRAM_2;
-	gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 2 )
-	gd->bd->bi_dram[2].start = WEP_SDRAM_3;
-	gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
-#endif
-#if ( CONFIG_NR_DRAM_BANKS > 3 )
-	gd->bd->bi_dram[3].start = WEP_SDRAM_4;
-	gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
-#endif
-
-	return 0;
-}
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
index 7dd2ea0..554915a 100644
--- a/board/xaeniax/Makefile
+++ b/board/xaeniax/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= xaeniax.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/xaeniax/config.mk b/board/xaeniax/config.mk
deleted file mode 100644
index c639752..0000000
--- a/board/xaeniax/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa3FB0000
-#CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S
deleted file mode 100644
index 57e1620..0000000
--- a/board/xaeniax/lowlevel_init.S
+++ /dev/null
@@ -1,424 +0,0 @@
- /*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	 r10, lr
-
-	/* Set up GPIO pins first ----------------------------------------- */
-
-	ldr	r0,=GPSR0
-	ldr	r1,=CONFIG_SYS_GPSR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPSR1
-	ldr	r1,=CONFIG_SYS_GPSR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPSR2
-	ldr	r1,=CONFIG_SYS_GPSR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR0
-	ldr	r1,=CONFIG_SYS_GPCR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR1
-	ldr	r1,=CONFIG_SYS_GPCR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPCR2
-	ldr	r1,=CONFIG_SYS_GPCR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR0
-	ldr	r1,=CONFIG_SYS_GPDR0_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR1
-	ldr	r1,=CONFIG_SYS_GPDR1_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GPDR2
-	ldr	r1,=CONFIG_SYS_GPDR2_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR0_L
-	ldr	r1,=CONFIG_SYS_GAFR0_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR0_U
-	ldr	r1,=CONFIG_SYS_GAFR0_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR1_L
-	ldr	r1,=CONFIG_SYS_GAFR1_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR1_U
-	ldr	r1,=CONFIG_SYS_GAFR1_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR2_L
-	ldr	r1,=CONFIG_SYS_GAFR2_L_VAL
-	str	r1,[r0]
-
-	ldr	r0,=GAFR2_U
-	ldr	r1,=CONFIG_SYS_GAFR2_U_VAL
-	str	r1,[r0]
-
-	ldr	r0,=PSSR		/* enable GPIO pins */
-	ldr	r1,=CONFIG_SYS_PSSR_VAL
-	str	r1,[r0]
-
-	/* ---------------------------------------------------------------- */
-	/* Enable memory interface                                          */
-	/*                                                                  */
-	/* The sequence below is based on the recommended init steps        */
-	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
-	/* Chapter 10.                                                      */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
-	/*         clocks to settle. Only necessary after hard reset...     */
-	/*         FIXME: can be optimized later                            */
-	/* ---------------------------------------------------------------- */
-
-	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-mem_init:
-
-	ldr	r1,=MEMC_BASE		/* get memory controller base addr. */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2a: Initialize Asynchronous static memory controller        */
-	/* ---------------------------------------------------------------- */
-
-	/* MSC registers: timing, bus width, mem type                       */
-
-	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC0_VAL
-	str     r2,[r1, #MSC0_OFFSET]
-	ldr     r2,[r1, #MSC0_OFFSET]	/* read back to ensure data latches */
-
-	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC1_VAL
-	str     r2,[r1, #MSC1_OFFSET]
-	ldr     r2,[r1, #MSC1_OFFSET]
-
-	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,=CONFIG_SYS_MSC2_VAL
-	str     r2,[r1, #MSC2_OFFSET]
-	ldr     r2,[r1, #MSC2_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2b: Initialize Card Interface                               */
-	/* ---------------------------------------------------------------- */
-
-	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,=CONFIG_SYS_MECR_VAL
-	str     r2,[r1, #MECR_OFFSET]
-	ldr	r2,[r1, #MECR_OFFSET]
-
-	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,=CONFIG_SYS_MCMEM0_VAL
-	str     r2,[r1, #MCMEM0_OFFSET]
-	ldr	r2,[r1, #MCMEM0_OFFSET]
-
-	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,=CONFIG_SYS_MCMEM1_VAL
-	str     r2,[r1, #MCMEM1_OFFSET]
-	ldr	r2,[r1, #MCMEM1_OFFSET]
-
-	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,=CONFIG_SYS_MCATT0_VAL
-	str     r2,[r1, #MCATT0_OFFSET]
-	ldr	r2,[r1, #MCATT0_OFFSET]
-
-	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,=CONFIG_SYS_MCATT1_VAL
-	str     r2,[r1, #MCATT1_OFFSET]
-	ldr	r2,[r1, #MCATT1_OFFSET]
-
-	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,=CONFIG_SYS_MCIO0_VAL
-	str     r2,[r1, #MCIO0_OFFSET]
-	ldr	r2,[r1, #MCIO0_OFFSET]
-
-	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,=CONFIG_SYS_MCIO1_VAL
-	str     r2,[r1, #MCIO1_OFFSET]
-	ldr	r2,[r1, #MCIO1_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
-	/* ---------------------------------------------------------------- */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
-	/* ---------------------------------------------------------------- */
-
-	@ get the mdrefr settings
-	ldr     r4,=CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	str     r4,[r1, #MDREFR_OFFSET]
-	ldr     r4,[r1, #MDREFR_OFFSET]
-
-	/* ---------------------------------------------------------------- */
-	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
-	/* ---------------------------------------------------------------- */
-
-	/* Initialize SXCNFG register. Assert the enable bits               */
-
-	/* Write SXMRS to cause an MRS command to all enabled banks of      */
-	/* synchronous static memory. Note that SXLCR need not be written   */
-	/* at this time.                                                    */
-
-	/* FIXME: we use async mode for now                                 */
-
-	/* ---------------------------------------------------------------- */
-	/* Step 4: Initialize SDRAM                                         */
-	/* ---------------------------------------------------------------- */
-
-	@ set K1RUN for bank 0
-	@
-	orr   r4,  r4,  #MDREFR_K1RUN
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic     r4,  r4,  #MDREFR_SLFRSH
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@ if E0PIN is also used:	 #(MDREFR_E1PIN|MDREFR_E0PIN)
-	orr     r4,  r4, #(MDREFR_E1PIN)
-
-	@ write back mdrefr
-	@
-	str     r4,  [r1, #MDREFR_OFFSET]
-	ldr     r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-
-	/* Step 4d:							*/
-	/* fetch platform value of mdcnfg				*/
-	@
-	ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str     r2,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
-	/*          100..200 µsec.                                          */
-
-	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
-					/* so 0x300 should be plenty        */
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-
-	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
-	/*          attempting non-burst read or write accesses to disabled */
-	/*          SDRAM, as commonly specified in the power up sequence   */
-	/*          documented in SDRAM data sheets. The address(es) used   */
-	/*          for this purpose must not be cacheable.                 */
-
-	ldr	r3,	=CONFIG_SYS_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-
-
-	/* Step 4g: Write MDCNFG with enable bits asserted                  */
-	/* get memory controller base address                               */
-	ldr     r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr     r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr     r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str     r3,  [r1, #MDCNFG_OFFSET]
-
-	/* Step 4h: Write MDMRS.                                            */
-
-	ldr     r2,	=CONFIG_SYS_MDMRS_VAL
-	str     r2,	[r1, #MDMRS_OFFSET]
-
-
-	/* We are finished with Intel's memory controller initialisation    */
-
-
-	/* ---------------------------------------------------------------- */
-	/* Disable (mask) all interrupts at interrupt controller            */
-	/* ---------------------------------------------------------------- */
-
-initirqs:
-	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
-	ldr     r2,  =ICLR
-	str     r1,  [r2]
-
-	ldr     r1,  =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
-	ldr     r2,  =ICMR
-	str     r1,  [r2]
-
-
-	/* ---------------------------------------------------------------- */
-	/* Clock initialisation                                             */
-	/* ---------------------------------------------------------------- */
-
-initclks:
-
-	/* Disable the peripheral clocks, and set the core clock frequency  */
-	/* (hard-coding at 398.12MHz for now).                              */
-	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
-	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
-	ldr     r1,  =CKEN
-	mov     r2,  #0
-	str     r2,  [r1]
-
-
-	/* default value						    */
-	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
-
-	/* ... and write the core clock config register                     */
-	ldr     r1,  =CCCR
-	str     r2,  [r1]
-
-#ifdef RTC
-	/* enable the 32Khz oscillator for RTC and PowerManager             */
-
-	ldr     r1,  =OSCC
-	mov     r2,  #OSCC_OON
-	str     r2,  [r1]
-
-	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
-	/* has settled.                                                     */
-60:
-	ldr     r2, [r1]
-	ands    r2, r2, #1
-	beq     60b
-#endif
-
-	@ Turn on needed clocks
-	@
-test:
-	ldr     r1,  =CKEN
-	ldr     r2,  =CONFIG_SYS_CKEN_VAL
-	str     r2,  [r1]
-
-	/* ---------------------------------------------------------------- */
-	/*                                                                  */
-	/* ---------------------------------------------------------------- */
-
-	/* Save SDRAM size ?*/
-	ldr	r1, =DRAM_SIZE
-	str	r8, [r1]
-
-	/* FIXME */
-
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0  /* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
-#endif
-
-	/* ---------------------------------------------------------------- */
-	/* End lowlevel_init                                                     */
-	/* ---------------------------------------------------------------- */
-
-endlowlevel_init:
-
-	mov     pc, lr
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
index 4c19c4d..40b0f3b 100644
--- a/board/xaeniax/xaeniax.c
+++ b/board/xaeniax/xaeniax.c
@@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init (void)
 {
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
 
 	/* arch number of xaeniax */
 	gd->bd->bi_arch_number = 585;
@@ -58,19 +59,18 @@ int board_late_init(void)
 	return 0;
 }
 
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-int dram_init (void)
+void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	/*	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
-	/*	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
-	/*	gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
-	/*	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
-	/*	gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
-	/*	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
-
-	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/xm250/Makefile b/board/xm250/Makefile
index a174f66..11e2b30 100644
--- a/board/xm250/Makefile
+++ b/board/xm250/Makefile
@@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= xm250.o flash.o
-SOBJS	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(OBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/xm250/config.mk b/board/xm250/config.mk
deleted file mode 100644
index a3fa0e5..0000000
--- a/board/xm250/config.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# MicroSys XM250 board:
-#
-
-
-# This is the address where U-Boot lives in flash:
-#CONFIG_SYS_TEXT_BASE = 0
-
-# FIXME: armboot does only work correctly when being compiled
-# for the addresses _after_ relocation to RAM!! Otherwhise the
-# .bss segment is assumed in flash...
-CONFIG_SYS_TEXT_BASE = 0xA3F80000
diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S
deleted file mode 100644
index 8230550..0000000
--- a/board/xm250/lowlevel_init.S
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc	p15,0,\reg,c2,c0,0
-	mov	\reg,\reg
-	sub	pc,pc,#4
-	.endm
-/*
-	.macro SET_LED val
-	ldr	r6, =CRADLE_LED_CLR_REG
-	ldr	r7, =0
-	str	r7, [r6]
-	ldr	r6, =CRADLE_LED_SET_REG
-	ldr	r7, =\val
-	str	r7, [r6]
-	.endm
-*/
-
-.globl lowlevel_init
-lowlevel_init:
-
-	mov	r10, lr
-
-	/* Set up GPIO pins first */
-
-	ldr	r0,   =GPSR0
-	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR1
-	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPSR2
-	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR0
-	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR1
-	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPCR2
-	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER0
-	ldr	r1,   =CONFIG_SYS_GRER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER1
-	ldr	r1,   =CONFIG_SYS_GRER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GRER2
-	ldr	r1,   =CONFIG_SYS_GRER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER0
-	ldr	r1,   =CONFIG_SYS_GFER0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER1
-	ldr	r1,   =CONFIG_SYS_GFER1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GFER2
-	ldr	r1,   =CONFIG_SYS_GFER2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR0
-	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR1
-	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GPDR2
-	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_L
-	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR0_U
-	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_L
-	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR1_U
-	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_L
-	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
-	str	r1,   [r0]
-
-	ldr	r0,   =GAFR2_U
-	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
-	str	r1,   [r0]
-
-	/* enable GPIO pins */
-	ldr	r0,   =PSSR
-	ldr	r1,   =CONFIG_SYS_PSSR_VAL
-	str	r1,   [r0]
-
-	/* SET_LED 1 */
-
-	ldr	r3, =MSC1		/* low - bank 2 Lubbock Registers / SRAM */
-	ldr	r2, =CONFIG_SYS_MSC1_VAL	/* high - bank 3 Ethernet Controller */
-	str	r2, [r3]		/* need to set MSC1 before trying to write to the HEX LEDs */
-	ldr	r2, [r3]		/* need to read it back to make sure the value latches (see MSC section of manual) */
-
-
-/*********************************************************************
- *  Initlialize Memory Controller
- *
- *  See PXA250 Operating System Developer's Guide
- *
- *  pause for 200 uSecs- allow internal clocks to settle
- *  *Note: only need this if hard reset... doing it anyway for now
- */
-
-	@ Step 1
-	@ ---- Wait 200 usec
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-	/* SET_LED 2 */
-
-mem_init:
-	@ get memory controller base address
-	ldr	r1,  =MEMC_BASE
-
-
-@****************************************************************************
-@  Step 2
-@
-
-	@ Step 2a
-	@ write msc0, read back to ensure data latches
-	@
-	ldr	r2,   =CONFIG_SYS_MSC0_VAL
-	str	r2,   [r1, #MSC0_OFFSET]
-	ldr	r2,   [r1, #MSC0_OFFSET]
-
-	@ write msc1
-	ldr	r2,  =CONFIG_SYS_MSC1_VAL
-	str	r2,  [r1, #MSC1_OFFSET]
-	ldr	r2,  [r1, #MSC1_OFFSET]
-
-	@ write msc2
-	ldr	r2,  =CONFIG_SYS_MSC2_VAL
-	str	r2,  [r1, #MSC2_OFFSET]
-	ldr	r2,  [r1, #MSC2_OFFSET]
-
-	@ Step 2b
-	@ write mecr
-	ldr	r2,  =CONFIG_SYS_MECR_VAL
-	str	r2,  [r1, #MECR_OFFSET]
-
-	@ write mcmem0
-	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
-	str	r2,  [r1, #MCMEM0_OFFSET]
-
-	@ write mcmem1
-	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
-	str	r2,  [r1, #MCMEM1_OFFSET]
-
-	@ write mcatt0
-	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
-	str	r2,  [r1, #MCATT0_OFFSET]
-
-	@ write mcatt1
-	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
-	str	r2,  [r1, #MCATT1_OFFSET]
-
-	@ write mcio0
-	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
-	str	r2,  [r1, #MCIO0_OFFSET]
-
-	@ write mcio1
-	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
-	str	r2,  [r1, #MCIO1_OFFSET]
-
-	/*SET_LED 3 */
-
-	@ Step 2c
-	@ fly-by-dma is defeatured on this part
-	@ write flycnfg
-	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
-	@str	r2,  [r1, #FLYCNFG_OFFSET]
-
-/* FIXME Does this sequence really make sense */
-#ifdef REDBOOT_WAY
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
-
-	@ extract DRI field (we need a valid DRI field)
-	@
-	ldr	r2,  =0xFFF
-
-	@ valid DRI field in r3
-	@
-	and	r3,  r3,  r2
-
-	@ get the reset state of MDREFR
-	@
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ clear the DRI field
-	@
-	bic	r4,  r4,  r2
-
-	@ insert the valid DRI field loaded above
-	@
-	orr	r4,  r4,  r3
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ *Note: preserve the mdrefr value in r4 *
-
-	/*SET_LED 4 */
-
-@****************************************************************************
-@  Step 3
-@
-@ NO SRAM
-
-	mov   pc, r10
-
-
-@****************************************************************************
-@  Step 4
-@
-
-	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
-
-	@ clear the free-running clock bits
-	@ (clear K0Free, K1Free, K2Free
-	@
-	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
-
-	@ set K0RUN for CPLD clock
-	@
-	orr	r4,  r4, #0x00002000
-
-	@ set K1RUN if bank 0 installed
-	@
-	orr	r4,  r4, #0x00010000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#else
-	@ Step 2d
-	@ get the mdrefr settings
-	ldr	r4,  =CONFIG_SYS_MDREFR_VAL
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@  Step 4
-
-	@ set K0RUN for FLASH clock
-	@
-	orr	r4,  r4, #0x00002000
-
-	@ set K1RUN for bank DRAM 0
-	@
-	orr	r4,  r4, #0x00010000
-
-	@ set K2RUN for bank PLD
-	@
-	orr	r4,  r4, #0x00040000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-
-	@ deassert SLFRSH
-	@
-	bic	r4,  r4,  #0x00400000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-
-	@ assert E1PIN
-	@
-	orr	r4,  r4,  #0x00008000
-
-	@ write back mdrefr
-	@
-	str	r4,  [r1, #MDREFR_OFFSET]
-	ldr	r4,  [r1, #MDREFR_OFFSET]
-	nop
-	nop
-#endif
-
-	@ Step 4d
-	@ fetch platform value of mdcnfg
-	@
-	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL
-
-	@ disable all sdram banks
-	@
-	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-	@ program banks 0/1 for bus width
-	@
-	bic	r2,  r2,  #MDCNFG_DWID0		@0=32-bit
-
-	@ write initial value of mdcnfg, w/o enabling sdram banks
-	@
-	str	r2,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4e
-	@ pause for 200 uSecs
-	@
-	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
-	mov	r2, #0
-	str	r2, [r3]
-	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
-1:
-	ldr	r2, [r3]
-	cmp	r4, r2
-	bgt	1b
-
-	/*SET_LED 5 */
-
-	/* Why is this here??? */
-	mov	r0, #0x78		@turn everything off
-	mcr	p15, 0, r0, c1, c0, 0	@(caches off, MMU off, etc.)
-
-	@ Step 4f
-	@ Access memory *not yet enabled* for CBR refresh cycles (8)
-	@ - CBR is generated for all banks
-
-	ldr	r2, =CONFIG_SYS_DRAM_BASE
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-	str	r2, [r2]
-
-	@ Step 4g
-	@get memory controller base address
-	@
-	ldr	r1,  =MEMC_BASE
-
-	@fetch current mdcnfg value
-	@
-	ldr	r3,  [r1, #MDCNFG_OFFSET]
-
-	@enable sdram bank 0 if installed (must do for any populated bank)
-	@
-	orr	r3,  r3,  #MDCNFG_DE0
-
-	@write back mdcnfg, enabling the sdram bank(s)
-	@
-	str	r3,  [r1, #MDCNFG_OFFSET]
-
-	@ Step 4h
-	@ write mdmrs
-	@
-	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
-	str	r2,  [r1, #MDMRS_OFFSET]
-
-	@ Done Memory Init
-
-	/*SET_LED 6 */
-
-	@********************************************************************
-	@ Disable (mask) all interrupts at the interrupt controller
-	@
-
-	@ clear the interrupt level register (use IRQ, not FIQ)
-	@
-	mov	r1, #0
-	ldr	r2,  =ICLR
-	str	r1,  [r2]
-
-	@ Set interrupt mask register
-	@
-	ldr	r1,  =CONFIG_SYS_ICMR_VAL
-	ldr	r2,  =ICMR
-	str	r1,  [r2]
-
-	@ ********************************************************************
-	@ Disable the peripheral clocks, and set the core clock
-	@
-
-	@ Turn Off ALL on-chip peripheral clocks for re-configuration
-	@
-	ldr	r1,  =CKEN
-	mov	r2,  #0
-	str	r2,  [r1]
-
-	@ set core clocks
-	@
-	ldr	r2,  =CONFIG_SYS_CCCR_VAL
-	ldr	r1,  =CCCR
-	str	r2,  [r1]
-
-#ifdef ENABLE32KHZ
-	@ enable the 32Khz oscillator for RTC and PowerManager
-	@
-	ldr	r1,  =OSCC
-	mov	r2,  #OSCC_OON
-	str	r2,  [r1]
-
-	@ NOTE:	 spin here until OSCC.OOK get set,
-	@	 meaning the PLL has settled.
-	@
-60:
-	ldr	r2, [r1]
-	ands	r2, r2, #1
-	beq	60b
-#endif
-
-	@ Turn on needed clocks
-	@
-	ldr	r1,  =CKEN
-	ldr	r2,  =CONFIG_SYS_CKEN_VAL
-	str	r2,  [r1]
-
-	/*SET_LED 7 */
-
-/* Is this needed???? */
-#define NODEBUG
-#ifdef NODEBUG
-	/*Disable software and data breakpoints */
-	mov	r0,#0
-	mcr	p15,0,r0,c14,c8,0	/* ibcr0 */
-	mcr	p15,0,r0,c14,c9,0	/* ibcr1 */
-	mcr	p15,0,r0,c14,c4,0	/* dbcon */
-
-	/*Enable all debug functionality */
-	mov	r0,#0x80000000
-	mcr	p14,0,r0,c10,c0,0	/* dcsr */
-
-#endif
-
-	/*SET_LED 8 */
-
-	mov	pc, r10
-
-@ End lowlevel_init
diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c
index 246bdde..3188cf2 100644
--- a/board/xm250/xm250.c
+++ b/board/xm250/xm250.c
@@ -56,6 +56,10 @@ int
 board_init (void)
 /**********************************************************/
 {
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
 	/* arch number of MicroSys XM250 */
 	gd->bd->bi_arch_number = MACH_TYPE_XM250;
 
@@ -65,21 +69,18 @@ board_init (void)
 	return 0;
 }
 
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
+	pxa_dram_init();
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
 
-	return (0);
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile
deleted file mode 100644
index fc23935..0000000
--- a/board/xsengine/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= xsengine.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/xsengine/config.mk b/board/xsengine/config.mk
deleted file mode 100644
index 821bb3b..0000000
--- a/board/xsengine/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xA3F80000
diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c
deleted file mode 100644
index 736905a..0000000
--- a/board/xsengine/flash.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define SWAP(x)               __swab32(x)
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Functions */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-			break;
-		case 1:
-			flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
-			break;
-		default:
-			panic ("configured too many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors */
-	flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
-	flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) return;
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
-			info->protect[i] = 0;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
-				break;
-	case FLASH_S29GL064M:	printf ("S29GL064M (64Mbit, top boot sector size)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
-	switch (value) {
-	case AMD_MANUFACT:
-		debug ("Manufacturer: AMD\n");
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		debug ("Manufacturer: FUJITSU\n");
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		debug ("Manufacturer: *** unknown ***\n");
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
-	switch (value) {
-
-	case AMD_ID_MIRROR:
-		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
-			addr[14], addr[15]);
-		switch(addr[14]) {
-		case AMD_ID_LV640U_2:
-			if (addr[15] != AMD_ID_LV640U_3) {
-				debug ("Chip: AMLV640U -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: AMLV640U\n");
-				info->flash_id += FLASH_AMLV640U;
-				info->sector_count = 128;
-				info->size = 0x01000000;
-			}
-			break;				/* => 16 MB	*/
-		case AMD_ID_GL064MT_2:
-			if (addr[15] != AMD_ID_GL064MT_3) {
-				debug ("Chip: S29GL064M-R3 -> unknown\n");
-				info->flash_id = FLASH_UNKNOWN;
-			} else {
-				debug ("Chip: S29GL064M-R3\n");
-				info->flash_id += FLASH_S29GL064M;
-				info->sector_count = 128;
-				info->size = 0x01000000;
-			}
-			break;				/* => 16 MB	*/
-		default:
-			debug ("Chip: *** unknown ***\n");
-			info->flash_id = FLASH_UNKNOWN;
-			break;
-		}
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	switch (value) {
-	case AMD_ID_MIRROR:
-		switch (info->flash_id & FLASH_TYPEMASK) {
-		/* only known types here - no default */
-		case FLASH_AMLV128U:
-		case FLASH_AMLV640U:
-		case FLASH_AMLV320U:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				base += 0x20000;
-			}
-			break;
-		case FLASH_AMLV320B:
-			for (i = 0; i < info->sector_count; i++) {
-				info->start[i] = base;
-				/*
-				 * The first 8 sectors are 8 kB,
-				 * all the other ones  are 64 kB
-				 */
-				base += (i < 8)
-					?  2 * ( 8 << 10)
-					:  2 * (64 << 10);
-			}
-			break;
-		}
-		break;
-
-	default:
-		return (0);
-		break;
-	}
-
-#if 0
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-#endif
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 100000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, SWAP(data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S
deleted file mode 100644
index 0d94ab6..0000000
--- a/board/xsengine/lowlevel_init.S
+++ /dev/null
@@ -1,221 +0,0 @@
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
-
-.globl lowlevel_init
-lowlevel_init:
-
-   mov      r10, lr
-
-/* ---- GPIO INITIALISATION ---- */
-/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
-
-   /* General purpose set registers */
-   ldr      r0,   =GPSR0
-   ldr      r1,   =CONFIG_SYS_GPSR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPSR1
-   ldr      r1,   =CONFIG_SYS_GPSR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPSR2
-   ldr      r1,   =CONFIG_SYS_GPSR2_VAL
-   str      r1,   [r0]
-
-   /* General purpose clear registers */
-   ldr      r0,   =GPCR0
-   ldr      r1,   =CONFIG_SYS_GPCR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPCR1
-   ldr      r1,   =CONFIG_SYS_GPCR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPCR2
-   ldr      r1,   =CONFIG_SYS_GPCR2_VAL
-   str      r1,   [r0]
-
-   /* General rising edge registers */
-   ldr      r0,   =GRER0
-   ldr      r1,   =CONFIG_SYS_GRER0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GRER1
-   ldr      r1,   =CONFIG_SYS_GRER1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GRER2
-   ldr      r1,   =CONFIG_SYS_GRER2_VAL
-   str      r1,   [r0]
-
-   /* General falling edge registers */
-   ldr      r0,   =GFER0
-   ldr      r1,   =CONFIG_SYS_GFER0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GFER1
-   ldr      r1,   =CONFIG_SYS_GFER1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GFER2
-   ldr      r1,   =CONFIG_SYS_GFER2_VAL
-   str      r1,   [r0]
-
-   /* General edge detect registers */
-   ldr      r0,   =GPDR0
-   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR1
-   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR2
-   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
-   str      r1,   [r0]
-
-   /* General alternate function registers */
-   ldr      r0,   =GAFR0_L		/* [0:15] */
-   ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR0_U		/* [31:16] */
-   ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR1_L		/* [47:32] */
-   ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR1_U		/* [63:48] */
-   ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR2_L		/* [79:64] */
-   ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GAFR2_U		/* [80] */
-   ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
-   str      r1,   [r0]
-
-   /* General purpose direction registers */
-   ldr      r0,   =GPDR0
-   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR1
-   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
-   str      r1,   [r0]
-   ldr      r0,   =GPDR2
-   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
-   str      r1,   [r0]
-
-   /* Power manager sleep status */
-   ldr      r0,   =PSSR
-   ldr      r1,   =CONFIG_SYS_PSSR_VAL
-   str      r1,   [r0]
-
-/* ---- MEMORY INITIALISATION ---- */
-/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
-/* pause for 200 uSecs- allow internal clocks to settle */
-   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300	/* really 0x2E1 is about 200usec, so 0x300 should be plenty */
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-mem_init:
-/* get memory controller base address */
-   ldr     r1,  =MEMC_BASE
-
-/* ---- FLASH INITIALISATION ---- */
-/* Write MSC0 and read back to ensure data change is accepted by cpu */
-   ldr     r2,   =CONFIG_SYS_MSC0_VAL
-   str     r2,   [r1, #MSC0_OFFSET]
-   ldr     r2,   [r1, #MSC0_OFFSET]
-
-/* ---- SDRAM INITIALISATION ---- */
-/* get the MDREFR settings */
-   ldr     r2,  =CONFIG_SYS_MDREFR_VAL
-   str     r2,  [r1, #MDREFR_OFFSET]
-
-/* fetch platform value of MDCNFG */
-   ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
-
-/* disable all sdram banks */
-   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
-   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
-
-/* write initial value of MDCNFG, w/o enabling sdram banks */
-   str     r2,  [r1, #MDCNFG_OFFSET]
-
-/* pause for 200 uSecs */
-   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
-   mov r2, #0
-   str r2, [r3]
-   ldr r4, =0x300	/* about 200 usec */
-1:
-   ldr r2, [r3]
-   cmp r4, r2
-   bgt 1b
-
-/* Access memory *not yet enabled* for CBR refresh cycles (8) */
-/* CBR is generated for all banks */
-
-   ldr     r2, =CONFIG_SYS_DRAM_BASE
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-   str     r2, [r2]
-
-/* get memory controller base address */
-   ldr     r2,  =MEMC_BASE
-
-/* Enable SDRAM bank 0 in MDCNFG register */
-   ldr     r2,  [r1, #MDCNFG_OFFSET]
-   orr     r2,  r2,  #MDCNFG_DE0
-   str     r2,  [r1, #MDCNFG_OFFSET]
-
-/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
-   ldr     r2,  =CONFIG_SYS_MDMRS_VAL
-   str     r2,  [r1, #MDMRS_OFFSET]
-
-/* ---- INTERRUPT INITIALISATION ---- */
-/* Disable (mask) all interrupts at the interrupt controller */
-/* clear the interrupt level register (use IRQ, not FIQ) */
-   mov     r1, #0
-   ldr     r2,  =ICLR
-   str     r1,  [r2]
-
-/* Set interrupt mask register */
-   ldr     r1,  =CONFIG_SYS_ICMR_VAL
-   ldr     r2,  =ICMR
-   str     r1,  [r2]
-
-/* ---- CLOCK INITIALISATION ---- */
-/* Disable the peripheral clocks, and set the core clock */
-
-/* Turn Off ALL on-chip peripheral clocks for re-configuration */
-   ldr     r1,  =CKEN
-   mov     r2,  #0
-   str     r2,  [r1]
-
-/* set core clocks */
-   ldr     r2,  =CONFIG_SYS_CCCR_VAL
-   ldr     r1,  =CCCR
-   str     r2,  [r1]
-
-#ifdef ENABLE32KHZ
-/* enable the 32Khz oscillator for RTC and PowerManager */
-   ldr     r1,  =OSCC
-   mov     r2,  #OSCC_OON
-   str     r2,  [r1]
-
-/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL has settled. */
-60:
-   ldr     r2, [r1]
-   ands    r2, r2, #1
-   beq     60b
-#endif
-
-/* Turn on needed clocks */
-   ldr     r1,  =CKEN
-   ldr     r2,  =CONFIG_SYS_CKEN_VAL
-   str     r2,  [r1]
-
-   mov   pc, r10
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
deleted file mode 100644
index 4464fd4..0000000
--- a/board/xsengine/xsengine.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* memory and cpu-speed are setup before relocation */
-	/* so we do _nothing_ here */
-
-	/* arch number */
-	gd->bd->bi_arch_number = MACH_TYPE_XSENGINE;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	return 0;
-}
-
-int board_late_init (void)
-{
-	setenv ("stdout", "serial");
-	setenv ("stderr", "serial");
-	return 0;
-}
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif