MLK-12436-17: imx: mx6sxauto: update board and header

Align with imx_v2015.04
Update pmic settings.
Update imximage.cfg.
Enable bmode.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

2 files changed, 80 insertions, 18 deletions

diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg
index 529e555..a4d10c1 100644
--- a/board/freescale/mx6sxsabreauto/imximage.cfg
+++ b/board/freescale/mx6sxsabreauto/imximage.cfg
@@ -1,7 +1,12 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
  */
 
 #define __ASSEMBLY__
@@ -16,7 +21,22 @@ IMAGE_VERSION 2
  * spi/sd/nand/onenand, qspi/nor
  */
 
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM	qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else
 BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sxsabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 
 /*
  * Device Configuration Data (DCD)
@@ -40,19 +60,20 @@ DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 DATA 4 0x020c4084 0xffffffff
 
-/* IOMUX - DDR IO Type */
+/* IOMUX */
+/* DDR IO TYPE */
 DATA 4 0x020e0618 0x000c0000
 DATA 4 0x020e05fc 0x00000000
 
-/* Clock */
+/* CLOCK */
 DATA 4 0x020e032c 0x00000030
 
-/* Address */
+/* ADDRESS */
 DATA 4 0x020e0300 0x00000030
 DATA 4 0x020e02fc 0x00000030
 DATA 4 0x020e05f4 0x00000030
 
-/* Control */
+/* CONTROL */
 DATA 4 0x020e0340 0x00000030
 
 DATA 4 0x020e0320 0x00000000
@@ -60,14 +81,14 @@ DATA 4 0x020e0310 0x00000030
 DATA 4 0x020e0314 0x00000030
 DATA 4 0x020e0614 0x00000030
 
-/* Data Strobe */
+/* DATA STROBE */
 DATA 4 0x020e05f8 0x00020000
 DATA 4 0x020e0330 0x00000030
 DATA 4 0x020e0334 0x00000030
 DATA 4 0x020e0338 0x00000030
 DATA 4 0x020e033c 0x00000030
 
-/* Data */
+/* DATA */
 DATA 4 0x020e0608 0x00020000
 DATA 4 0x020e060c 0x00000030
 DATA 4 0x020e0610 0x00000030
@@ -78,10 +99,10 @@ DATA 4 0x020e02f0 0x00000030
 DATA 4 0x020e02f4 0x00000030
 DATA 4 0x020e02f8 0x00000030
 
-/* Calibrations - ZQ */
+/* Calibrations */
+/* ZQ */
 DATA 4 0x021b0800 0xa1390003
-
-/* Write leveling */
+/* write leveling */
 DATA 4 0x021b080c 0x002C003D
 DATA 4 0x021b0810 0x00110046
 
@@ -101,10 +122,11 @@ DATA 4 0x021b0820 0x33333333
 DATA 4 0x021b0824 0x33333333
 DATA 4 0x021b0828 0x33333333
 
-/* Complete calibration by forced measurement */
+/* Complete calibration by forced measurment */
 DATA 4 0x021b08b8 0x00000800
 
-/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+/* MMDC init */
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
 DATA 4 0x021b0004 0x0002002d
 DATA 4 0x021b0008 0x00333030
 DATA 4 0x021b000c 0x676b52f3
@@ -117,7 +139,8 @@ DATA 4 0x021b0030 0x006b1023
 DATA 4 0x021b0040 0x0000007f
 DATA 4 0x021b0000 0x85190000
 
-/* Initialize MT41K256M16HA-125 - MR2 */
+/* Initialize CS0: MT41K256M16HA-125 */
+/* MR2 */
 DATA 4 0x021b001c 0x04008032
 /* MR3 */
 DATA 4 0x021b001c 0x00008033
@@ -128,9 +151,11 @@ DATA 4 0x021b001c 0x05208030
 /* DDR device ZQ calibration */
 DATA 4 0x021b001c 0x04008040
 
-/* Final DDR setup, before operation start */
+/* final DDR setup, before operation start */
 DATA 4 0x021b0020 0x00000800
 DATA 4 0x021b0818 0x00022227
 DATA 4 0x021b0004 0x0002556d
 DATA 4 0x021b0404 0x00011006
 DATA 4 0x021b001c 0x00000000
+
+#endif
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index ed4cced..a61a210 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -59,6 +59,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define I2C_PMIC	1
 
+#define BUTTON_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE | \
+	PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_40ohm)
+
 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
 			PAD_CTL_SRE_FAST)
@@ -254,11 +257,45 @@ struct i2c_pads_info i2c_pad_info3 = {
 
 int power_init_board(void)
 {
-	struct pmic *p;
-
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
+	struct pmic *pfuze;
+	unsigned int reg;
+	int ret;
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
 		return -ENODEV;
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW1AB standby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
+
+	/* set SW1C standby volatage 1.10V */
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(11000);
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+	/* Enable power of VGEN5 3V3, needed for SD3 */
+	pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
+	reg &= ~LDO_VOL_MASK;
+	reg |= (LDOB_3_30V | (1 << LDO_EN));
+	pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
 
 	return 0;
 }