Merge branch 'master' of git://www.denx.de/git/u-boot-imx

11 files changed, 680 insertions, 259 deletions

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 0e9b506..e58c03c 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -682,125 +682,6 @@ int checkboard(void)
 #include <spl.h>
 #include <libfdt.h>
 
-const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
-	.dram_sdclk_0 =  0x00020030,
-	.dram_sdclk_1 =  0x00020030,
-	.dram_cas =  0x00020030,
-	.dram_ras =  0x00020030,
-	.dram_reset =  0x00020030,
-	.dram_sdcke0 =  0x00003000,
-	.dram_sdcke1 =  0x00003000,
-	.dram_sdba2 =  0x00000000,
-	.dram_sdodt0 =  0x00003030,
-	.dram_sdodt1 =  0x00003030,
-	.dram_sdqs0 =  0x00000030,
-	.dram_sdqs1 =  0x00000030,
-	.dram_sdqs2 =  0x00000030,
-	.dram_sdqs3 =  0x00000030,
-	.dram_sdqs4 =  0x00000030,
-	.dram_sdqs5 =  0x00000030,
-	.dram_sdqs6 =  0x00000030,
-	.dram_sdqs7 =  0x00000030,
-	.dram_dqm0 =  0x00020030,
-	.dram_dqm1 =  0x00020030,
-	.dram_dqm2 =  0x00020030,
-	.dram_dqm3 =  0x00020030,
-	.dram_dqm4 =  0x00020030,
-	.dram_dqm5 =  0x00020030,
-	.dram_dqm6 =  0x00020030,
-	.dram_dqm7 =  0x00020030,
-};
-
-const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
-	.dram_sdclk_0 =  0x00000030,
-	.dram_sdclk_1 =  0x00000030,
-	.dram_cas =  0x00000030,
-	.dram_ras =  0x00000030,
-	.dram_reset =  0x00000030,
-	.dram_sdcke0 =  0x00003000,
-	.dram_sdcke1 =  0x00003000,
-	.dram_sdba2 =  0x00000000,
-	.dram_sdodt0 =  0x00003030,
-	.dram_sdodt1 =  0x00003030,
-	.dram_sdqs0 =  0x00000030,
-	.dram_sdqs1 =  0x00000030,
-	.dram_sdqs2 =  0x00000030,
-	.dram_sdqs3 =  0x00000030,
-	.dram_sdqs4 =  0x00000030,
-	.dram_sdqs5 =  0x00000030,
-	.dram_sdqs6 =  0x00000030,
-	.dram_sdqs7 =  0x00000030,
-	.dram_dqm0 =  0x00000030,
-	.dram_dqm1 =  0x00000030,
-	.dram_dqm2 =  0x00000030,
-	.dram_dqm3 =  0x00000030,
-	.dram_dqm4 =  0x00000030,
-	.dram_dqm5 =  0x00000030,
-	.dram_dqm6 =  0x00000030,
-	.dram_dqm7 =  0x00000030,
-};
-
-const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
-	.grp_ddr_type =  0x000C0000,
-	.grp_ddrmode_ctl =  0x00020000,
-	.grp_ddrpke =  0x00000000,
-	.grp_addds =  0x00000030,
-	.grp_ctlds =  0x00000030,
-	.grp_ddrmode =  0x00020000,
-	.grp_b0ds =  0x00000030,
-	.grp_b1ds =  0x00000030,
-	.grp_b2ds =  0x00000030,
-	.grp_b3ds =  0x00000030,
-	.grp_b4ds =  0x00000030,
-	.grp_b5ds =  0x00000030,
-	.grp_b6ds =  0x00000030,
-	.grp_b7ds =  0x00000030,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 =  0x001F001F,
-	.p0_mpwldectrl1 =  0x001F001F,
-	.p1_mpwldectrl0 =  0x00440044,
-	.p1_mpwldectrl1 =  0x00440044,
-	.p0_mpdgctrl0 =  0x434B0350,
-	.p0_mpdgctrl1 =  0x034C0359,
-	.p1_mpdgctrl0 =  0x434B0350,
-	.p1_mpdgctrl1 =  0x03650348,
-	.p0_mprddlctl =  0x4436383B,
-	.p1_mprddlctl =  0x39393341,
-	.p0_mpwrdlctl =  0x35373933,
-	.p1_mpwrdlctl =  0x48254A36,
-};
-
-const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
-	.p0_mpwldectrl0 =  0x001B001E,
-	.p0_mpwldectrl1 =  0x002E0029,
-	.p1_mpwldectrl0 =  0x001B002A,
-	.p1_mpwldectrl1 =  0x0019002C,
-	.p0_mpdgctrl0 =  0x43240334,
-	.p0_mpdgctrl1 =  0x0324031A,
-	.p1_mpdgctrl0 =  0x43340344,
-	.p1_mpdgctrl1 =  0x03280276,
-	.p0_mprddlctl =  0x44383A3E,
-	.p1_mprddlctl =  0x3C3C3846,
-	.p0_mpwrdlctl =  0x2E303230,
-	.p1_mpwrdlctl =  0x38283E34,
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg mem_ddr = {
-	.mem_speed = 1600,
-	.density = 2,
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 14,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-};
-
 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -831,44 +712,209 @@ static void gpr_init(void)
 	}
 }
 
-/*
- * This section requires the differentiation between iMX6 Sabre boards, but
- * for now, it will configure only for the mx6q variant.
- */
-static void spl_dram_init(void)
+static int mx6q_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x43270338,
+	0x021b0840, 0x03200314,
+	0x021b483c, 0x431A032F,
+	0x021b4840, 0x03200263,
+	0x021b0848, 0x4B434748,
+	0x021b4848, 0x4445404C,
+	0x021b0850, 0x38444542,
+	0x021b4850, 0x4935493A,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x555A7975,
+	0x021b0010, 0xFF538F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0000, 0x831A0000,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static int mx6qp_dcd_table[] = {
+	0x020e0798, 0x000c0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001b001e,
+	0x021b0810, 0x002e0029,
+	0x021b480c, 0x001b002a,
+	0x021b4810, 0x0019002c,
+	0x021b083c, 0x43240334,
+	0x021b0840, 0x0324031a,
+	0x021b483c, 0x43340344,
+	0x021b4840, 0x03280276,
+	0x021b0848, 0x44383A3E,
+	0x021b4848, 0x3C3C3846,
+	0x021b0850, 0x2e303230,
+	0x021b4850, 0x38283E34,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08c0, 0x24912249,
+	0x021b48c0, 0x24914289,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x24444040,
+	0x021b000c, 0x555A7955,
+	0x021b0010, 0xFF320F64,
+	0x021b0014, 0x01ff00db,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0400, 0x14420000,
+	0x021b0000, 0x831A0000,
+	0x021b0890, 0x00400C58,
+	0x00bb0008, 0x00000000,
+	0x00bb000c, 0x2891E41A,
+	0x00bb0038, 0x00000564,
+	0x00bb0014, 0x00000040,
+	0x00bb0028, 0x00000020,
+	0x00bb002c, 0x00000020,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static void ddr_init(int *table, int size)
 {
-	struct mx6_ddr_sysinfo sysinfo = {
-		/* width of data bus:0=16,1=32,2=64 */
-		.dsize = 2,
-		/* config for full 4GB range so that get_mem_size() works */
-		.cs_density = 32, /* 32Gb per CS */
-		/* single chip select */
-		.ncs = 1,
-		.cs1_mirror = 0,
-		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
-		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
-		.walat = 1,	/* Write additional latency */
-		.ralat = 5,	/* Read additional latency */
-		.mif3_mode = 3,	/* Command prediction working mode */
-		.bi_on = 1,	/* Bank interleaving enabled */
-		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-		.ddr_type = DDR_TYPE_DDR3,
-		.refsel = 1,	/* Refresh cycles at 32KHz */
-		.refr = 7,	/* 8 refresh commands per refresh cycle */
-	};
+	int i;
 
-	if (is_mx6dqp()) {
-		mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
-		mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
-	} else {
-		mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-		mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
-	}
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dq())
+		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+	else if (is_mx6dqp())
+		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
 }
 
 void board_init_f(ulong dummy)
 {
+	/* DDR initialization */
+	spl_dram_init();
+
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
@@ -884,9 +930,6 @@ void board_init_f(ulong dummy)
 	/* UART clocks enabled and gd valid - init serial console */
 	preloader_console_init();
 
-	/* DDR initialization */
-	spl_dram_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig
new file mode 100644
index 0000000..7eec497
--- /dev/null
+++ b/board/freescale/mx6ullevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6ULL_14X14_EVK
+
+config SYS_BOARD
+	default "mx6ullevk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6ullevk"
+
+endif
diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS
new file mode 100644
index 0000000..4137674
--- /dev/null
+++ b/board/freescale/mx6ullevk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6ULLEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6ullevk/
+F:	include/configs/mx6ullevk.h
+F:	configs/mx6ull_14x14_evk_defconfig
diff --git a/board/freescale/mx6ullevk/Makefile b/board/freescale/mx6ullevk/Makefile
new file mode 100644
index 0000000..c64fba4
--- /dev/null
+++ b/board/freescale/mx6ullevk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ullevk.o
diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg
new file mode 100644
index 0000000..4604b62
--- /dev/null
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM	qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ullevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x000C0030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000004
+DATA 4 0x021B083C 0x41640158
+DATA 4 0x021B0848 0x40403237
+DATA 4 0x021B0850 0x40403C33
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00944009
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
new file mode 100644
index 0000000..489bf21
--- /dev/null
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", "EVK");
+	setenv("board_rev", "14X14");
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6ULL 14x14 EVK\n");
+
+	return 0;
+}
diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig
index d67a69a..212f994 100644
--- a/board/phytec/pcm052/Kconfig
+++ b/board/phytec/pcm052/Kconfig
@@ -12,4 +12,28 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "pcm052"
 
+config PCM052_DDR_SIZE
+	int
+	default 256
+
+endif
+
+if TARGET_BK4R1
+
+config SYS_BOARD
+	default "pcm052"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_SOC
+	default "vf610"
+
+config SYS_CONFIG_NAME
+	default "bk4r1"
+
+config PCM052_DDR_SIZE
+	int
+	default 512
+
 endif
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index e4f61e1..e75ff4f 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -152,57 +152,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {
 
 int dram_init(void)
 {
-	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
-		.tinit             = 5,
-		.trst_pwron        = 80000,
-		.cke_inactive      = 200000,
-		.wrlat             = 5,
-		.caslat_lin        = 12,
-		.trc               = 6,
-		.trrd              = 4,
-		.tccd              = 4,
-		.tbst_int_interval = 4,
-		.tfaw              = 18,
-		.trp               = 6,
-		.twtr              = 4,
-		.tras_min          = 15,
-		.tmrd              = 4,
-		.trtp              = 4,
-		.tras_max          = 14040,
-		.tmod              = 12,
-		.tckesr            = 4,
-		.tcke              = 3,
-		.trcd_int          = 6,
-		.tras_lockout      = 1,
-		.tdal              = 10,
-		.bstlen            = 3,
-		.tdll              = 512,
-		.trp_ab            = 6,
-		.tref              = 1542,
-		.trfc              = 64,
-		.tref_int          = 5,
-		.tpdex             = 3,
-		.txpdll            = 10,
-		.txsnr             = 68,
-		.txsr              = 506,
-		.cksrx             = 5,
-		.cksre             = 5,
-		.freq_chg_en       = 1,
-		.zqcl              = 256,
-		.zqinit            = 512,
-		.zqcs              = 64,
-		.ref_per_zq        = 64,
-		.zqcs_rotate       = 1,
-		.aprebit           = 10,
-		.cmd_age_cnt       = 255,
-		.age_cnt           = 255,
-		.q_fullness        = 0,
-		.odt_rd_mapcs0     = 1,
-		.odt_wr_mapcs0     = 1,
-		.wlmrd             = 40,
-		.wldqsen           = 25,
-	};
-
 	static const iomux_v3_cfg_t pcm052_pads[] = {
 		PCM052_VF610_PAD_DDR_A15__DDR_A_15,
 		PCM052_VF610_PAD_DDR_A14__DDR_A_14,
@@ -256,11 +205,126 @@ int dram_init(void)
 		PCM052_VF610_PAD_DDR_RESETB,
 	};
 
-	imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
+#if defined(CONFIG_TARGET_PCM052)
+
+	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 6,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 4,
+		.tfaw              = 18,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 14040,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 1,
+		.tdal              = 10,
+		.bstlen            = 3,
+		.tdll              = 512,
+		.trp_ab            = 6,
+		.tref              = 1542,
+		.trfc              = 64,
+		.tref_int          = 5,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 68,
+		.txsr              = 506,
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 1,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 1,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 255,
+		.age_cnt           = 255,
+		.q_fullness        = 0,
+		.odt_rd_mapcs0     = 1,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
 
 	ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
 			     pcm052_phy_settings, 1, 2);
 
+#elif defined(CONFIG_TARGET_BK4R1)
+
+	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 6,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 0,
+		.tfaw              = 16,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 28080,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 1,
+		.tdal              = 12,
+		.bstlen            = 3,
+		.tdll              = 512,
+		.trp_ab            = 6,
+		.tref              = 3120,
+		.trfc              = 104,
+		.tref_int          = 0,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 108,
+		.txsr              = 512,
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 1,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 1,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 255,
+		.age_cnt           = 255,
+		.q_fullness        = 0,
+		.odt_rd_mapcs0     = 1,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
+
+	ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
+			     pcm052_phy_settings, 1, 1);
+
+#else /* Unknown PCM052 variant */
+
+#error DDR characteristics undefined for this target. Please define them.
+
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
+
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 
 	return 0;
@@ -513,3 +577,41 @@ int checkboard(void)
 
 	return 0;
 }
+
+static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	ulong addr;
+
+	/* Consume 'm4go' */
+	argc--; argv++;
+
+	/*
+	 * Parse provided address - default to load_addr in case not provided.
+	 */
+
+	if (argc)
+		addr = simple_strtoul(argv[0], NULL, 16);
+	else
+		addr = load_addr;
+
+	/*
+	 * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0]
+	 */
+	writel(addr + 0x401, 0x4006E028);
+
+	/*
+	 * Start secondary processor by enabling its clock
+	 */
+	writel(0x15a5a, 0x4006B08C);
+
+	return 1;
+}
+
+U_BOOT_CMD(
+	m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go,
+	"start the secondary Cortex-M4 from scatter file image",
+	"[<addr>]\n"
+	"    - start secondary Cortex-M4 core using a scatter file image\n"
+	"The argument needs to be a scatter file\n"
+);
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 8eedd65..c64e31e 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -12,17 +12,17 @@
 #include <asm/gpio.h>
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <fsl_esdhc.h>
-#include <i2c.h>
 #include <linux/sizes.h>
 #include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <power/pmic.h>
+#include <power/rn5t567_pmic.h>
 #include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -38,9 +38,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 
-#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
-	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
 	PAD_CTL_DSE_3P3V_49OHM)
 
@@ -48,36 +45,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
-		.gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
-		.gp = IMX_GPIO_NR(1, 4),
-	},
-	.sda = {
-		.i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
-		.gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
-		.gp = IMX_GPIO_NR(1, 5),
-	},
-};
-/* I2C4 for Colibri I2C */
-static struct i2c_pads_info i2c_pad_info4 = {
-	.scl = {
-		.i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC,
-		.gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC,
-		.gp = IMX_GPIO_NR(7, 8),
-	},
-	.sda = {
-		.i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC,
-		.gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC,
-		.gp = IMX_GPIO_NR(7, 9),
-	},
-};
-#endif
-
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -331,11 +298,6 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 
-#ifdef CONFIG_SYS_I2C_MXC
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
-#endif
-
 	return 0;
 }
 
@@ -377,6 +339,46 @@ int board_late_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int reg, ver;
+	int ret;
+
+
+	ret = pmic_get("rn5t567", &dev);
+	if (ret)
+		return ret;
+	ver = pmic_reg_read(dev, RN5T567_LSIVER);
+	reg = pmic_reg_read(dev, RN5T567_OTPVER);
+
+	printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
+
+	/* set judge and press timer of N_OE to minimal values */
+	pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	struct udevice *dev;
+
+	pmic_get("rn5t567", &dev);
+
+	/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
+	pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
+	pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
+
+	/*
+	 * Re-power factor detection on PMIC side is not instant. 1ms
+	 * proved to be enough time until reset takes effect.
+	 */
+	mdelay(1);
+}
+#endif
+
 int checkboard(void)
 {
 	printf("Model: Toradex Colibri iMX7%c\n",
@@ -408,13 +410,3 @@ int board_ehci_hcd_init(int port)
 	return 0;
 }
 #endif
-
-static struct mxc_serial_platdata mxc_serial_plat = {
-	.reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
-	.use_dte = true,
-};
-
-U_BOOT_DEVICE(mxc_serial) = {
-	.name = "serial_mxc",
-	.platdata = &mxc_serial_plat,
-};
diff --git a/board/udoo/README b/board/udoo/README
new file mode 100644
index 0000000..6fbcc59
--- /dev/null
+++ b/board/udoo/README
@@ -0,0 +1,21 @@
+How to use U-Boot on MX6Q/DL Udoo boards
+----------------------------------------
+
+- Build U-Boot for MX6Q/DL Udoo boards:
+
+$ make mrproper
+$ make udoo_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Insert the SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index c513b22..a21a3d0 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -188,7 +188,7 @@ static struct mx6_ddr_sysinfo mem_q = {
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
@@ -231,7 +231,7 @@ static struct mx6_ddr_sysinfo mem_dl = {
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 /* DDR 32bit 512MB */
@@ -250,7 +250,7 @@ static struct mx6_ddr_sysinfo mem_s = {
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 static void ccgr_init(void)