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authorStefano Babic <sbabic@denx.de>2014-08-08 10:18:40 +0200
committerStefano Babic <sbabic@denx.de>2014-08-08 10:18:40 +0200
commitc23154aab5825fec81d5500c53eaa686646c76b5 (patch)
tree32b0aafae49f664a65ced50981492bb031f006b8 /board
parentcb07d74e2e0c0a41533b6bcd551af9bf2ebcf2bc (diff)
parent9d195a546179bc732aba9eacccf0a9a3db591288 (diff)
downloadu-boot-imx-c23154aab5825fec81d5500c53eaa686646c76b5.zip
u-boot-imx-c23154aab5825fec81d5500c53eaa686646c76b5.tar.gz
u-boot-imx-c23154aab5825fec81d5500c53eaa686646c76b5.tar.bz2
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'board')
-rw-r--r--board/bf527-ezkit/video.c10
-rw-r--r--board/bf548-ezkit/video.c10
-rw-r--r--board/cm-bf548/video.c10
-rw-r--r--board/esd/common/cmd_loadpci.c8
-rw-r--r--board/freescale/m5253demo/flash.c10
-rw-r--r--board/gaisler/gr_cpci_ax2000/u-boot.lds143
-rw-r--r--board/gaisler/gr_ep2s60/u-boot.lds143
-rw-r--r--board/gaisler/gr_xc3s_1500/u-boot.lds145
-rw-r--r--board/gaisler/grsim/u-boot.lds144
-rw-r--r--board/gaisler/grsim_leon2/u-boot.lds142
-rw-r--r--board/gumstix/pepper/board.c30
-rw-r--r--board/mpl/common/kbd.c6
-rw-r--r--board/mpl/common/kbd.h6
-rw-r--r--board/mpl/pati/pati.c8
-rw-r--r--board/nokia/rx51/rx51.c6
-rw-r--r--board/raspberrypi/rpi_b/rpi_b.c4
-rw-r--r--board/renesas/alt/Makefile9
-rw-r--r--board/renesas/alt/alt.c173
-rw-r--r--board/renesas/alt/qos.c944
-rw-r--r--board/renesas/alt/qos.h12
-rw-r--r--board/sunxi/Makefile4
-rw-r--r--board/sunxi/board.c67
-rw-r--r--board/sunxi/dram_a13_oli_micro.c32
-rw-r--r--board/sunxi/dram_cubieboard.c31
-rw-r--r--board/sunxi/dram_cubieboard2.c31
-rw-r--r--board/sunxi/dram_r7dongle.c31
-rw-r--r--board/sunxi/gmac.c11
-rw-r--r--board/ti/am335x/board.c30
-rw-r--r--board/ti/am43xx/board.c14
-rw-r--r--board/ti/dra7xx/evm.c7
-rw-r--r--board/ti/dra7xx/mux_data.h12
-rw-r--r--board/ti/k2hk_evm/Makefile9
-rw-r--r--board/ti/k2hk_evm/ddr3.c268
-rw-r--r--board/ti/ks2_evm/Makefile13
-rw-r--r--board/ti/ks2_evm/README_K2HK (renamed from board/ti/k2hk_evm/README)28
-rw-r--r--board/ti/ks2_evm/board.c (renamed from board/ti/k2hk_evm/board.c)156
-rw-r--r--board/ti/ks2_evm/board.h19
-rw-r--r--board/ti/ks2_evm/board_k2e.c39
-rw-r--r--board/ti/ks2_evm/board_k2hk.c81
-rw-r--r--board/ti/ks2_evm/ddr3_cfg.c170
-rw-r--r--board/ti/ks2_evm/ddr3_cfg.h24
-rw-r--r--board/ti/ks2_evm/ddr3_k2e.c55
-rw-r--r--board/ti/ks2_evm/ddr3_k2hk.c84
-rw-r--r--board/xilinx/zynq/Makefile3
44 files changed, 1963 insertions, 1219 deletions
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
index 5d8a091..c2bf145 100644
--- a/board/bf527-ezkit/video.c
+++ b/board/bf527-ezkit/video.c
@@ -391,14 +391,6 @@ void video_stop(void)
#endif
}
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
int drv_video_init(void)
{
int error, devices = 1;
@@ -448,8 +440,6 @@ int drv_video_init(void)
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
error = stdio_register(&videodev);
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
index 6737ac1..47e68c6 100644
--- a/board/bf548-ezkit/video.c
+++ b/board/bf548-ezkit/video.c
@@ -281,14 +281,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
}
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
int drv_video_init(void)
{
int error, devices = 1;
@@ -338,8 +330,6 @@ int drv_video_init(void)
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
error = stdio_register(&videodev);
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
index c35d285..b098615 100644
--- a/board/cm-bf548/video.c
+++ b/board/cm-bf548/video.c
@@ -283,14 +283,6 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
}
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
int drv_video_init(void)
{
int error, devices = 1;
@@ -342,8 +334,6 @@ int drv_video_init(void)
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
error = stdio_register(&videodev);
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index 803179a..95d1891 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -12,9 +12,6 @@
#endif
#if defined(CONFIG_CMD_BSP)
-
-extern int do_source (cmd_tbl_t *, int, int, char *[]);
-
#define ADDRMASK 0xfffff000
/*
@@ -27,7 +24,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int count2 = 0;
char addr[16];
char str[] = "\\|/-";
- char *local_args[2];
u32 la, ptm1la;
#if defined(CONFIG_440)
@@ -84,9 +80,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
* Boot image via "source" command
*/
printf("executing script at addr 0x%s ...\n", addr);
- local_args[0] = addr;
- local_args[1] = NULL;
- do_source(cmdtp, 0, 1, local_args);
+ source(la, NULL);
break;
case 2:
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 16bba59..071701d 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -56,14 +56,16 @@ ulong flash_init(void)
int flash_get_offsets(ulong base, flash_info_t * info)
{
- int j, k;
+ int i;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
info->start[0] = base;
- for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
- info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
- info->protect[k] = 0;
+ info->protect[0] = 0;
+ for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+ info->start[i] = info->start[i - 1]
+ + CONFIG_SYS_SST_SECTSZ;
+ info->protect[i] = 0;
}
}
diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds
deleted file mode 100644
index 6d9c90c..0000000
--- a/board/gaisler/gr_cpci_ax2000/u-boot.lds
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's GR-CPCI-AX2000 board
- * with template design.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds
deleted file mode 100644
index 973603c..0000000
--- a/board/gaisler/gr_ep2s60/u-boot.lds
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's Template design
- * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds
deleted file mode 100644
index 1ed71f2..0000000
--- a/board/gaisler/gr_xc3s_1500/u-boot.lds
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's GR-XC3S-1500 board
- * with template design.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds
deleted file mode 100644
index cdc8394..0000000
--- a/board/gaisler/grsim/u-boot.lds
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's GRSIM LEON3 simulator.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds
deleted file mode 100644
index 1f038bc..0000000
--- a/board/gaisler/grsim_leon2/u-boot.lds
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Linker script for Gaisler Research AB's GRSIM LEON2 simulator.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon2/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c
index 75aac49..f644f81 100644
--- a/board/gumstix/pepper/board.c
+++ b/board/gumstix/pepper/board.c
@@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
index 1b5487b..99de2ca 100644
--- a/board/mpl/common/kbd.c
+++ b/board/mpl/common/kbd.c
@@ -204,8 +204,6 @@ int drv_isa_kbd_init (void)
memset (&kbddev, 0, sizeof(kbddev));
strcpy(kbddev.name, DEVNAME);
kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- kbddev.putc = NULL ;
- kbddev.puts = NULL ;
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
@@ -250,7 +248,7 @@ void kbd_put_queue(char data)
}
/* test if a character is in the queue */
-int kbd_testc(void)
+int kbd_testc(struct stdio_dev *dev)
{
if(in_pointer==out_pointer)
return(0); /* no data */
@@ -258,7 +256,7 @@ int kbd_testc(void)
return(1);
}
/* gets the character from the queue */
-int kbd_getc(void)
+int kbd_getc(struct stdio_dev *dev)
{
char c;
while(in_pointer==out_pointer);
diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h
index 7b19b37..b549e20 100644
--- a/board/mpl/common/kbd.h
+++ b/board/mpl/common/kbd.h
@@ -8,8 +8,10 @@
#ifndef _KBD_H_
#define _KBD_H_
-extern int kbd_testc(void);
-extern int kbd_getc(void);
+struct stdio_dev;
+
+int kbd_testc(struct stdio_dev *sdev);
+int kbd_getc(struct stdio_dev *sdev);
extern void kbd_interrupt(void);
extern char *kbd_initialize(void);
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
index 8ca9bb3..5d701a7 100644
--- a/board/mpl/pati/pati.c
+++ b/board/mpl/pati/pati.c
@@ -445,7 +445,7 @@ void pci_con_put_it(const char c)
PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
}
-void pci_con_putc(const char c)
+void pci_con_putc(struct stdio_dev *dev, const char c)
{
pci_con_put_it(c);
if(c == '\n')
@@ -453,7 +453,7 @@ void pci_con_putc(const char c)
}
-int pci_con_getc(void)
+int pci_con_getc(struct stdio_dev *dev)
{
int res;
int diff;
@@ -473,14 +473,14 @@ int pci_con_getc(void)
return res;
}
-int pci_con_tstc(void)
+int pci_con_tstc(struct stdio_dev *dev)
{
if(r_ptr==(volatile int)w_ptr)
return 0;
return 1;
}
-void pci_con_puts (const char *s)
+void pci_con_puts(struct stdio_dev *dev, const char *s)
{
while (*s) {
pci_con_putc(*s);
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 3e419ef..c2e07db 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -585,7 +585,7 @@ static void rx51_kp_fill(u8 k, u8 mods)
* Routine: rx51_kp_tstc
* Description: Test if key was pressed (from buffer).
*/
-int rx51_kp_tstc(void)
+int rx51_kp_tstc(struct stdio_dev *sdev)
{
u8 c, r, dk, i;
u8 intr;
@@ -641,10 +641,10 @@ int rx51_kp_tstc(void)
* Routine: rx51_kp_getc
* Description: Get last pressed key (from buffer).
*/
-int rx51_kp_getc(void)
+int rx51_kp_getc(struct stdio_dev *sdev)
{
keybuf_head %= KEYBUF_SIZE;
- while (!rx51_kp_tstc())
+ while (!rx51_kp_tstc(sdev))
WATCHDOG_RESET();
return keybuf[keybuf_head++];
}
diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c
index f33fae9..220bb90 100644
--- a/board/raspberrypi/rpi_b/rpi_b.c
+++ b/board/raspberrypi/rpi_b/rpi_b.c
@@ -16,7 +16,9 @@
#include <common.h>
#include <config.h>
+#include <fdt_support.h>
#include <lcd.h>
+#include <mmc.h>
#include <asm/arch/mbox.h>
#include <asm/arch/sdhci.h>
#include <asm/global_data.h>
@@ -91,7 +93,7 @@ int board_init(void)
return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
}
-int board_mmc_init(void)
+int board_mmc_init(bd_t *bis)
{
ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
int ret;
diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile
new file mode 100644
index 0000000..9ed12bd
--- /dev/null
+++ b/board/renesas/alt/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := alt.o qos.o
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
new file mode 100644
index 0000000..9d8e8f9
--- /dev/null
+++ b/board/renesas/alt/alt.c
@@ -0,0 +1,173 @@
+/*
+ * board/renesas/alt/alt.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* QoS */
+ qos_init();
+}
+
+#define MSTPSR1 0xE6150038
+#define SMSTPCR1 0xE6150134
+#define TMU0_MSTP125 (1 << 25)
+
+#define MSTPSR7 0xE61501C4
+#define SMSTPCR7 0xE615014C
+#define SCIF0_MSTP719 (1 << 19)
+
+#define MSTPSR8 0xE61509A0
+#define SMSTPCR8 0xE6150990
+#define ETHER_MSTP813 (1 << 13)
+
+#define mstp_setbits(type, addr, saddr, set) \
+ out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+ out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+ mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+ mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+ /* TMU */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
+
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+ return 0;
+}
+
+void arch_preboot_os(void)
+{
+ /* Disable TMU0 */
+ mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7794_pinmux_init();
+
+ /* Ether Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ8, NULL);
+
+ /* PHY reset */
+ gpio_request(GPIO_GP_1_24, NULL);
+ gpio_direction_output(GPIO_GP_1_24, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_1_24, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ u8 val;
+
+ i2c_set_bus_num(1); /* PowerIC connected to ch3 */
+ i2c_init(400000, 0);
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c
new file mode 100644
index 0000000..ea51f3f
--- /dev/null
+++ b/board/renesas/alt/qos.c
@@ -0,0 +1,944 @@
+/*
+ * board/renesas/alt/qos.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.10 */
+
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x1F0D0B0A, &s3c->s3crorr);
+ writel(0x1F0D0B09, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x80928092, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x0000207D, &qos_addr->dbtmval0);
+ writel(0x00002053, &qos_addr->dbtmval1);
+ writel(0x0000202A, &qos_addr->dbtmval2);
+ writel(0x00001FBD, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002064, &qos_addr->dbthres0);
+ writel(0x0000203E, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x0000207D, &qos_addr->dbtmval0);
+ writel(0x00002053, &qos_addr->dbtmval1);
+ writel(0x00002043, &qos_addr->dbtmval2);
+ writel(0x00002030, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002064, &qos_addr->dbthres0);
+ writel(0x0000203E, &qos_addr->dbthres1);
+ writel(0x00002031, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+ writel(0x00780080, &mxi->mxsaar0);
+ writel(0x02000800, &mxi->mxsaar1);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000E, &mxi_qos->du0);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
diff --git a/board/renesas/alt/qos.h b/board/renesas/alt/qos.h
new file mode 100644
index 0000000..9a6c046
--- /dev/null
+++ b/board/renesas/alt/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index cbf8f08..62acb8f 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,4 +10,8 @@
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
+obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
+obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
+obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index b05d0b9..2179e23 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -12,10 +12,19 @@
*/
#include <common.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/io.h>
+#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -106,15 +115,73 @@ int board_mmc_init(bd_t *bis)
}
#endif
+void i2c_init_board(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+ clock_twi_onoff(0, 1);
+}
+
#ifdef CONFIG_SPL_BUILD
void sunxi_board_init(void)
{
+ int power_failed = 0;
unsigned long ramsize;
+#ifdef CONFIG_AXP152_POWER
+ power_failed = axp152_init();
+ power_failed |= axp152_set_dcdc2(1400);
+ power_failed |= axp152_set_dcdc3(1500);
+ power_failed |= axp152_set_dcdc4(1250);
+ power_failed |= axp152_set_ldo2(3000);
+#endif
+#ifdef CONFIG_AXP209_POWER
+ power_failed |= axp209_init();
+ power_failed |= axp209_set_dcdc2(1400);
+ power_failed |= axp209_set_dcdc3(1250);
+ power_failed |= axp209_set_ldo2(3000);
+ power_failed |= axp209_set_ldo3(2800);
+ power_failed |= axp209_set_ldo4(2800);
+#endif
+
printf("DRAM:");
ramsize = sunxi_dram_init();
printf(" %lu MiB\n", ramsize >> 20);
if (!ramsize)
hang();
+
+ /*
+ * Only clock up the CPU to full speed if we are reasonably
+ * assured it's being powered with suitable core voltage
+ */
+ if (!power_failed)
+ clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+ else
+ printf("Failed to set core voltage! Can't set CPU frequency\n");
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ if (!getenv("ethaddr")) {
+ uint32_t reg_val = readl(SUNXI_SID_BASE);
+
+ if (reg_val) {
+ uint8_t mac_addr[6];
+
+ mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
+ mac_addr[1] = (reg_val >> 0) & 0xff;
+ reg_val = readl(SUNXI_SID_BASE + 0x0c);
+ mac_addr[2] = (reg_val >> 24) & 0xff;
+ mac_addr[3] = (reg_val >> 16) & 0xff;
+ mac_addr[4] = (reg_val >> 8) & 0xff;
+ mac_addr[5] = (reg_val >> 0) & 0xff;
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+ }
+
+ return 0;
}
#endif
diff --git a/board/sunxi/dram_a13_oli_micro.c b/board/sunxi/dram_a13_oli_micro.c
new file mode 100644
index 0000000..8154ea2
--- /dev/null
+++ b/board/sunxi/dram_a13_oli_micro.c
@@ -0,0 +1,32 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 408,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 256,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0x10,
+ .emr3 = 0,
+
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_cubieboard.c b/board/sunxi/dram_cubieboard.c
new file mode 100644
index 0000000..399028c
--- /dev/null
+++ b/board/sunxi/dram_cubieboard.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_cubieboard2.c b/board/sunxi/dram_cubieboard2.c
new file mode 100644
index 0000000..9e75367
--- /dev/null
+++ b/board/sunxi/dram_cubieboard2.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0x0,
+ .tpr4 = 0x1,
+ .tpr5 = 0x0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_r7dongle.c b/board/sunxi/dram_r7dongle.c
new file mode 100644
index 0000000..59343cb
--- /dev/null
+++ b/board/sunxi/dram_r7dongle.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 384,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 8,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x04,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index e48328d..e7ff952 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -16,17 +16,28 @@ int sunxi_gmac_initialize(bd_t *bis)
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
/* Set MII clock */
+#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+ CCM_GMAC_CTRL_GPIT_MII);
+#endif
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
+#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
+#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#else
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
}
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index da780ed..d81eec9 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 7e239f1..51fa9e0 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,6 +19,7 @@
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "board.h"
+#include <power/pmic.h>
#include <power/tps65218.h>
#include <miiphy.h>
#include <cpsw.h>
@@ -605,6 +606,19 @@ void sdram_init(void)
}
#endif
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ power_tps65218_init(I2C_PMIC);
+ p = pmic_get("TPS65218_PMIC");
+ if (p && !pmic_probe(p))
+ puts("PMIC: TPS65218\n");
+
+ return 0;
+}
+
int board_init(void)
{
struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 7f19655..ae50d88 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -163,6 +163,8 @@ int spl_start_uboot(void)
#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+extern u32 *const omap_si_rev;
+
static void cpsw_control(int enabled)
{
/* VTP can be added here */
@@ -189,7 +191,7 @@ static struct cpsw_platform_data cpsw_data = {
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
- .slaves = 1,
+ .slaves = 2,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
@@ -260,6 +262,9 @@ int board_eth_init(bd_t *bis)
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
+ if (*omap_si_rev == DRA722_ES1_0)
+ cpsw_data.active_slave = 1;
+
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index c9e202a..7db7032 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -56,6 +56,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{RGMII0_RXD2, (IEN | M0) },
{RGMII0_RXD1, (IEN | M0) },
{RGMII0_RXD0, (IEN | M0) },
+ {VIN2A_D12, (M3) },
+ {VIN2A_D13, (M3) },
+ {VIN2A_D14, (M3) },
+ {VIN2A_D15, (M3) },
+ {VIN2A_D16, (M3) },
+ {VIN2A_D17, (M3) },
+ {VIN2A_D18, (IEN | M3)},
+ {VIN2A_D19, (IEN | M3)},
+ {VIN2A_D20, (IEN | M3)},
+ {VIN2A_D21, (IEN | M3)},
+ {VIN2A_D22, (IEN | M3)},
+ {VIN2A_D23, (IEN | M3)},
{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/k2hk_evm/Makefile
deleted file mode 100644
index 3645f2f..0000000
--- a/board/ti/k2hk_evm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# K2HK-EVM: board Makefile
-# (C) Copyright 2012-2014
-# Texas Instruments Incorporated, <www.ti.com>
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += board.o
-obj-y += ddr3.o
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
deleted file mode 100644
index 6092eb8..0000000
--- a/board/ti/k2hk_evm/ddr3.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1600_64A = {
- .pllcr = 0x0001C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0D861A80ul,
- .ptr4 = 0x0C827100ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0xA19DBB66ul,
- .dtpr1 = 0x12868300ul,
- .dtpr2 = 0x50035200ul,
- .mr0 = 0x00001C70ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
- .dtcr = 0x730035C7ul,
- .pgcr2 = 0x00F07A12ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_64 = {
- .sdcfg = 0x6200CE6aul,
- .sdtim1 = 0x16709C55ul,
- .sdtim2 = 0x00001D4Aul,
- .sdtim3 = 0x435DFF54ul,
- .sdtim4 = 0x553F0CFFul,
- .zqcfg = 0xF0073200ul,
- .sdrfc = 0x00001869ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1600_32 = {
- .pllcr = 0x0001C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0D861A80ul,
- .ptr4 = 0x0C827100ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0xA19DBB66ul,
- .dtpr1 = 0x12868300ul,
- .dtpr2 = 0x50035200ul,
- .mr0 = 0x00001C70ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
- .dtcr = 0x730035C7ul,
- .pgcr2 = 0x00F07A12ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_32 = {
- .sdcfg = 0x6200DE6aul,
- .sdtim1 = 0x16709C55ul,
- .sdtim2 = 0x00001D4Aul,
- .sdtim3 = 0x435DFF54ul,
- .sdtim4 = 0x553F0CFFul,
- .zqcfg = 0x70073200ul,
- .sdrfc = 0x00001869ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64A = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
- NOSRA_MASK | UDIMM_MASK),
- .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_64 = {
- .sdcfg = 0x62008C62ul,
- .sdtim1 = 0x125C8044ul,
- .sdtim2 = 0x00001D29ul,
- .sdtim3 = 0x32CDFF43ul,
- .sdtim4 = 0x543F0ADFul,
- .zqcfg = 0xF0073200ul,
- .sdrfc = 0x00001457ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1333_32 = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
- NOSRA_MASK | UDIMM_MASK),
- .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_32 = {
- .sdcfg = 0x62009C62ul,
- .sdtim1 = 0x125C8044ul,
- .sdtim2 = 0x00001D29ul,
- .sdtim3 = 0x32CDFF43ul,
- .sdtim4 = 0x543F0ADFul,
- .zqcfg = 0xf0073200ul,
- .sdrfc = 0x00001457ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64 = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-/******************************************************/
-int get_dimm_params(char *dimm_name)
-{
- u8 spd_params[256];
- int ret;
- int old_bus;
-
- i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
- old_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
- i2c_set_bus_num(old_bus);
-
- dimm_name[0] = '\0';
-
- if (ret) {
- puts("Cannot read DIMM params\n");
- return 1;
- }
-
- /*
- * We need to convert spd data to dimm parameters
- * and to DDR3 EMIF and PHY regirsters values.
- * For now we just return DIMM type string value.
- * Caller may use this value to choose appropriate
- * a pre-set DDR3 configuration
- */
-
- strncpy(dimm_name, (char *)&spd_params[0x80], 18);
- dimm_name[18] = '\0';
-
- return 0;
-}
-
-struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
-struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
-struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
-struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
-
-void init_ddr3(void)
-{
- char dimm_name[32];
-
- get_dimm_params(dimm_name);
-
- printf("Detected SO-DIMM [%s]\n", dimm_name);
-
- if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
- init_pll(&ddr3a_400);
- if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
- printf("DRAM: Capacity 8 GiB (includes reported below)\n");
- } else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
- printf("DRAM: Capacity 4 GiB (includes reported below)\n");
- }
- } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
- init_pll(&ddr3a_333);
- if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
- } else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
- }
- } else {
- printf("Unknown SO-DIMM. Cannot configure DDR3\n");
- while (1)
- ;
- }
-
- init_pll(&ddr3b_333);
- init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
- init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
-}
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
new file mode 100644
index 0000000..00f1164
--- /dev/null
+++ b/board/ti/ks2_evm/Makefile
@@ -0,0 +1,13 @@
+#
+# KS2-EVM: board Makefile
+# (C) Copyright 2012-2014
+# Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += ddr3_cfg.o
+obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
diff --git a/board/ti/k2hk_evm/README b/board/ti/ks2_evm/README_K2HK
index bfeb05b..7426b8d 100644
--- a/board/ti/k2hk_evm/README
+++ b/board/ti/ks2_evm/README_K2HK
@@ -38,11 +38,13 @@ board configuration file: include/configs/k2hk_evm.h
Supported boot modes:
- SPI NOR boot
+ - AEMIF NAND boot
Supported image formats:-
- u-boot.bin: for loading and running u-boot.bin through Texas instruments
code composure studio (CCS)
- u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+ - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
Build instructions:
===================
@@ -55,6 +57,10 @@ To build u-boot-spi.gph
>make k2hk_evm_config
>make u-boot-spi.gph
+To build u-boot-nand.gph
+ >make k2hk_evm_config
+ >make u-boot-nand.gph
+
Load and Run U-Boot on K2HK EVM using CCS
=========================================
@@ -115,8 +121,28 @@ instructions:-
5. At the U-Boot console type following to setup u-boot environment variables.
setenv addr_uboot 0x87000000
setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
- run burn_uboot
+ run burn_uboot_spi
Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
to "SPI Little Endian Boot mode" as per instruction at
http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
+
+AEMIF NAND Flash programming instructions
+======================================
+U-Boot image can be flashed to first 1024KB of the NAND flash using following
+instructions:-
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+ CortexA15_1 (Free Running)"
+3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+ using CCS", but using address 0x87000000.
+4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+ setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
+ run burn_uboot_nand
+ Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+ to "ARM NAND Boot mode" as per instruction at
+ http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
diff --git a/board/ti/k2hk_evm/board.c b/board/ti/ks2_evm/board.c
index ef90f9d..dfe7be6 100644
--- a/board/ti/k2hk_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -1,45 +1,22 @@
/*
- * K2HK EVM : Board initialization
+ * Keystone : Board initialization
*
- * (C) Copyright 2012-2014
+ * (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "board.h"
#include <common.h>
#include <exports.h>
#include <fdt_support.h>
-#include <libfdt.h>
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
+#include <asm/arch/ddr3.h>
#include <asm/arch/emac_defs.h>
-#include <asm/arch/psc_defs.h>
#include <asm/ti-common/ti-aemif.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 device_big_endian;
-
-unsigned int external_clk[ext_clk_count] = {
- [sys_clk] = 122880000,
- [alt_core_clk] = 125000000,
- [pa_clk] = 122880000,
- [tetris_clk] = 125000000,
- [ddr3a_clk] = 100000000,
- [ddr3b_clk] = 100000000,
- [mcm_clk] = 312500000,
- [pcie_clk] = 100000000,
- [sgmii_srio_clk] = 156250000,
- [xgmii_clk] = 156250000,
- [usb_clk] = 100000000,
- [rp1_clk] = 123456789 /* TODO: cannot find
- what is that */
-};
-
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = AEMIF_MODE_NAND,
@@ -52,18 +29,11 @@ static struct aemif_config aemif_configs[] = {
.turn_around = 3,
.width = AEMIF_WIDTH_8,
},
-
-};
-
-static struct pll_init_data pll_config[] = {
- CORE_PLL_1228,
- PASS_PLL_983,
- TETRIS_PLL_1200,
};
int dram_init(void)
{
- init_ddr3();
+ ddr3_init();
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
@@ -71,42 +41,18 @@ int dram_init(void)
return 0;
}
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
- {
- .int_name = "K2HK_EMAC",
- .rx_flow = 22,
- .phy_addr = 0,
- .slave_port = 1,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- },
- {
- .int_name = "K2HK_EMAC1",
- .rx_flow = 23,
- .phy_addr = 1,
- .slave_port = 2,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- },
- {
- .int_name = "K2HK_EMAC2",
- .rx_flow = 24,
- .phy_addr = 2,
- .slave_port = 3,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- },
- {
- .int_name = "K2HK_EMAC3",
- .rx_flow = 25,
- .phy_addr = 3,
- .slave_port = 4,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- },
-};
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
int get_eth_env_param(char *env_name)
{
char *env;
- int res = -1;
+ int res = -1;
env = getenv(env_name);
if (env)
@@ -117,12 +63,14 @@ int get_eth_env_param(char *env_name)
int board_eth_init(bd_t *bis)
{
- int j;
- int res;
- char link_type_name[32];
+ int j;
+ int res;
+ int port_num;
+ char link_type_name[32];
- for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
- j++) {
+ port_num = get_num_eth_ports();
+
+ for (j = 0; j < port_num; j++) {
sprintf(link_type_name, "sgmii%d_link_type", j);
res = get_eth_env_param(link_type_name);
if (res >= 0)
@@ -135,46 +83,24 @@ int board_eth_init(bd_t *bis)
}
#endif
-/* Byte swap the 32-bit data if the device is BE */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
- u32 i;
-
- if (device_big_endian)
- for (i = 0; i < length; i++, ptr++)
- *ptr = __swab32(*ptr);
-
- return 0;
-}
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void)
-{
- init_plls(ARRAY_SIZE(pll_config), pll_config);
- return 0;
-}
-#endif
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-#define K2_DDR3_START_ADDR 0x80000000
void ft_board_setup(void *blob, bd_t *bd)
{
- u64 start[2];
+ int lpae;
+ char *env;
+ char *endp;
+ int nbanks;
u64 size[2];
- char name[32], *env, *endp;
- int lpae, nodeoffset;
+ u64 start[2];
+ char name[32];
+ int nodeoffset;
u32 ddr3a_size;
- int nbanks;
+ int unitrd_fixup = 0;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
+ env = getenv("uinitrd_fixup");
+ unitrd_fixup = env && simple_strtol(env, NULL, 0);
ddr3a_size = 0;
if (lpae) {
@@ -191,7 +117,7 @@ void ft_board_setup(void *blob, bd_t *bd)
/* adjust memory start address for LPAE */
if (lpae) {
- start[0] -= K2_DDR3_START_ADDR;
+ start[0] -= CONFIG_SYS_SDRAM_BASE;
start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
}
@@ -217,10 +143,11 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, start, size, nbanks);
/* Fix up the initrd */
- if (lpae) {
- u64 initrd_start, initrd_end;
- u32 *prop1, *prop2;
+ if (lpae && unitrd_fixup) {
int err;
+ u32 *prop1, *prop2;
+ u64 initrd_start, initrd_end;
+
nodeoffset = fdt_path_offset(blob, "/chosen");
if (nodeoffset >= 0) {
prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
@@ -229,11 +156,11 @@ void ft_board_setup(void *blob, bd_t *bd)
"linux,initrd-end", NULL);
if (prop1 && prop2) {
initrd_start = __be32_to_cpu(*prop1);
- initrd_start -= K2_DDR3_START_ADDR;
+ initrd_start -= CONFIG_SYS_SDRAM_BASE;
initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_start = __cpu_to_be64(initrd_start);
initrd_end = __be32_to_cpu(*prop2);
- initrd_end -= K2_DDR3_START_ADDR;
+ initrd_end -= CONFIG_SYS_SDRAM_BASE;
initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
initrd_end = __cpu_to_be64(initrd_end);
@@ -267,9 +194,10 @@ void ft_board_setup(void *blob, bd_t *bd)
void ft_board_setup_ex(void *blob, bd_t *bd)
{
- int lpae;
- char *env;
- u64 *reserve_start, size;
+ int lpae;
+ u64 size;
+ char *env;
+ u64 *reserve_start;
env = getenv("mem_lpae");
lpae = env && simple_strtol(env, NULL, 0);
@@ -286,7 +214,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
*reserve_start = __cpu_to_be64(*reserve_start);
size = __cpu_to_be64(*(reserve_start + 1));
if (size) {
- *reserve_start -= K2_DDR3_START_ADDR;
+ *reserve_start -= CONFIG_SYS_SDRAM_BASE;
*reserve_start +=
CONFIG_SYS_LPAE_SDRAM_BASE;
*reserve_start =
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
new file mode 100644
index 0000000..d91ef73
--- /dev/null
+++ b/board/ti/ks2_evm/board.h
@@ -0,0 +1,19 @@
+/*
+ * K2HK EVM : Board common header
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KS2_BOARD
+#define _KS2_BOARD
+
+#include <asm/arch/emac_defs.h>
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int get_num_eth_ports(void);
+
+#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
new file mode 100644
index 0000000..d2499b7
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -0,0 +1,39 @@
+/*
+ * K2E EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 100000000,
+ [alt_core_clk] = 100000000,
+ [pa_clk] = 100000000,
+ [ddr3_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+};
+
+static struct pll_init_data pll_config[] = {
+ CORE_PLL_1200,
+ PASS_PLL_1000,
+};
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ init_plls(ARRAY_SIZE(pll_config), pll_config);
+ return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
new file mode 100644
index 0000000..a369d6b
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -0,0 +1,81 @@
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 125000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 125000000,
+ [ddr3a_clk] = 100000000,
+ [ddr3b_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_srio_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+ [rp1_clk] = 123456789
+};
+
+static struct pll_init_data pll_config[] = {
+ CORE_PLL_1228,
+ PASS_PLL_983,
+ TETRIS_PLL_1200,
+};
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2HK_EMAC",
+ .rx_flow = 22,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC1",
+ .rx_flow = 23,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC2",
+ .rx_flow = 24,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2HK_EMAC3",
+ .rx_flow = 25,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ init_plls(ARRAY_SIZE(pll_config), pll_config);
+ return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
new file mode 100644
index 0000000..f7da9f2
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -0,0 +1,170 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <i2c.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR3 PHY configuration data with 1600M rate, 8GB size */
+struct ddr3_phy_config ddr3phy_1600_8g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0xA19DBB66ul,
+ .dtpr1 = 0x32868300ul,
+ .dtpr2 = 0x50035200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x730035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
+struct ddr3_emif_config ddr3_1600_8g = {
+ .sdcfg = 0x6200CE6Aul,
+ .sdtim1 = 0x16709C55ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF54ul,
+ .sdtim4 = 0x553F0CFFul,
+ .zqcfg = 0xF0073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+#ifdef CONFIG_K2HK_EVM
+/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
+struct ddr3_phy_config ddr3phy_1333_2g = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x32857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
+struct ddr3_emif_config ddr3_1333_2g = {
+ .sdcfg = 0x62008C62ul,
+ .sdtim1 = 0x125C8044ul,
+ .sdtim2 = 0x00001D29ul,
+ .sdtim3 = 0x32CDFF43ul,
+ .sdtim4 = 0x543F0ADFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001457ul,
+};
+#endif
+
+#ifdef CONFIG_K2E_EVM
+/* DDR3 PHY configuration data with 1600M rate, and 4GB size */
+struct ddr3_phy_config ddr3phy_1600_4g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x08861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x9D9CBB66ul,
+ .dtpr1 = 0x12840300ul,
+ .dtpr2 = 0x5002D200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */
+struct ddr3_emif_config ddr3_1600_4g = {
+ .sdcfg = 0x6200CE62ul,
+ .sdtim1 = 0x166C9855ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x421DFF53ul,
+ .sdtim4 = 0x543F07FFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+#endif
+
+int ddr3_get_dimm_params(char *dimm_name)
+{
+ int ret;
+ int old_bus;
+ u8 spd_params[256];
+
+ i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+ old_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+ i2c_set_bus_num(old_bus);
+
+ dimm_name[0] = '\0';
+
+ if (ret) {
+ puts("Cannot read DIMM params\n");
+ return 1;
+ }
+
+ /*
+ * We need to convert spd data to dimm parameters
+ * and to DDR3 EMIF and PHY regirsters values.
+ * For now we just return DIMM type string value.
+ * Caller may use this value to choose appropriate
+ * a pre-set DDR3 configuration
+ */
+
+ strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+ dimm_name[18] = '\0';
+
+ return 0;
+}
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
new file mode 100644
index 0000000..15fcf52
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -0,0 +1,24 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR3_CFG_H
+#define __DDR3_CFG_H
+
+extern struct ddr3_phy_config ddr3phy_1600_8g;
+extern struct ddr3_emif_config ddr3_1600_8g;
+
+extern struct ddr3_phy_config ddr3phy_1333_2g;
+extern struct ddr3_emif_config ddr3_1333_2g;
+
+extern struct ddr3_phy_config ddr3phy_1600_4g;
+extern struct ddr3_emif_config ddr3_1600_4g;
+
+int ddr3_get_dimm_params(char *dimm_name);
+
+#endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
new file mode 100644
index 0000000..40fd966
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -0,0 +1,55 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+ char dimm_name[32];
+
+ if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
+ init_pll(&ddr3_400);
+
+ ddr3_get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ /* 8G SO-DIMM */
+ ddr3_size = 8;
+ printf("DRAM: 8 GiB\n");
+ ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
+ } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
+ /* 4G SO-DIMM */
+ ddr3_size = 4;
+ printf("DRAM: 4 GiB\n");
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
+ }
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
new file mode 100644
index 0000000..21a5a0a
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -0,0 +1,84 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+
+void ddr3_init(void)
+{
+ char dimm_name[32];
+
+ ddr3_get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ init_pll(&ddr3a_400);
+ if (cpu_revision() > 0) {
+ if (cpu_revision() > 1) {
+ /* PG 2.0 */
+ /* Reset DDR3A PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+ ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1600_8g);
+ } else {
+ /* PG 1.1 */
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1600_8g);
+ }
+
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_8g);
+ printf("DRAM: Capacity 8 GiB (includes reported below)\n");
+ } else {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+ ddr3_1600_8g.sdcfg |= 0x1000;
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_8g);
+ printf("DRAM: Capacity 4 GiB (includes reported below)\n");
+ }
+ } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
+ init_pll(&ddr3a_333);
+ if (cpu_revision() > 0) {
+ if (cpu_revision() > 1) {
+ /* PG 2.0 */
+ /* Reset DDR3A PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+ ddr3phy_1333_2g.zq0cr1 |= 0x10000;
+ ddr3phy_1333_2g.zq1cr1 |= 0x10000;
+ ddr3phy_1333_2g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1333_2g);
+ } else {
+ /* PG 1.1 */
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1333_2g);
+ }
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_2g);
+ } else {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
+ ddr3_1333_2g.sdcfg |= 0x1000;
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_2g);
+ }
+ } else {
+ printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+ while (1)
+ ;
+ }
+}
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index fd93f63..71c0c35 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -10,3 +10,6 @@ obj-y := board.o
# Please copy ps7_init.c/h from hw project to this directory
obj-$(CONFIG_SPL_BUILD) += \
$(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes