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authorTom Rini <trini@konsulko.com>2016-07-12 08:15:17 -0400
committerTom Rini <trini@konsulko.com>2016-07-12 08:15:17 -0400
commitb8e599746cac1833328bc3a8e37eeefe346baf90 (patch)
treeec49cc9ac3c8638fe11774e945cf0bcc4e87c1f4 /board
parentbff97dde8c8cf6fd5f04bb26fca83f61eadc1741 (diff)
parent9532fe3b40ddf66ef976dee3d5cf1d8b3396bf4d (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-x86
Diffstat (limited to 'board')
-rw-r--r--board/advantech/Kconfig28
-rw-r--r--board/advantech/som-db5800-som-6867/.gitignore3
-rw-r--r--board/advantech/som-db5800-som-6867/Kconfig28
-rw-r--r--board/advantech/som-db5800-som-6867/MAINTAINERS7
-rw-r--r--board/advantech/som-db5800-som-6867/Makefile8
-rw-r--r--board/advantech/som-db5800-som-6867/acpi/mainboard.asl11
-rw-r--r--board/advantech/som-db5800-som-6867/dsdt.asl14
-rw-r--r--board/advantech/som-db5800-som-6867/som-db5800-som-6867.c24
-rw-r--r--board/advantech/som-db5800-som-6867/start.S9
-rw-r--r--board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c2
10 files changed, 134 insertions, 0 deletions
diff --git a/board/advantech/Kconfig b/board/advantech/Kconfig
new file mode 100644
index 0000000..a8d4969
--- /dev/null
+++ b/board/advantech/Kconfig
@@ -0,0 +1,28 @@
+if VENDOR_ADVANTECH
+
+choice
+ prompt "Mainboard model"
+ optional
+
+config TARGET_SOM_DB5800_SOM_6867
+ bool "Advantech SOM-DB5800 & SOM-6867"
+ help
+ Advantech SOM-DB5800 COM Express development board with SOM-6867
+ installed.
+
+ SOM-6867 is a COM Express Type 6 Compact Module with either an Intel
+ Atom E3845 or Celeron N2920 processor.
+
+ SOM-DB5800 is a COM Express Development board with:
+ 10/100/1000 Ethernet
+ PCIe slots
+ 4x USB ports
+ HDMI/DisplayPort/DVI, LVDS, VGA
+ SATA ports
+ ALC892 HD Audio Codec
+
+endchoice
+
+source "board/advantech/som-db5800-som-6867/Kconfig"
+
+endif
diff --git a/board/advantech/som-db5800-som-6867/.gitignore b/board/advantech/som-db5800-som-6867/.gitignore
new file mode 100644
index 0000000..6eb8a54
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig
new file mode 100644
index 0000000..f6f3748
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_SOM_DB5800_SOM_6867
+
+config SYS_BOARD
+ default "som-db5800-som-6867"
+
+config SYS_VENDOR
+ default "advantech"
+
+config SYS_SOC
+ default "baytrail"
+
+config SYS_CONFIG_NAME
+ default "som-db5800-som-6867"
+
+config SYS_TEXT_BASE
+ default 0xfff00000 if !EFI_STUB
+ default 0x01110000 if EFI_STUB
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR if !EFI_STUB
+ select INTEL_BAYTRAIL
+ select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+ default 0xe0000000
+
+endif
diff --git a/board/advantech/som-db5800-som-6867/MAINTAINERS b/board/advantech/som-db5800-som-6867/MAINTAINERS
new file mode 100644
index 0000000..92989bf
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/MAINTAINERS
@@ -0,0 +1,7 @@
+Advantech SOM-DB5800-SOM-6867
+M: George McCollister <george.mccollister@gmail.com>
+S: Maintained
+F: board/advantech/som-db5800-som-6867
+F: include/configs/som-db5800-som-6867.h
+F: configs/som-db5800-som-6867_defconfig
+F: arch/x86/dts/baytrail_som-db5800-som-6867.dts
diff --git a/board/advantech/som-db5800-som-6867/Makefile b/board/advantech/som-db5800-som-6867/Makefile
new file mode 100644
index 0000000..9837aa0
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2015, Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += som-db5800-som-6867.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/advantech/som-db5800-som-6867/acpi/mainboard.asl b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl
new file mode 100644
index 0000000..21785ea
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+ Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/advantech/som-db5800-som-6867/dsdt.asl b/board/advantech/som-db5800-som-6867/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+ /* platform specific */
+ #include <asm/arch/acpi/platform.asl>
+
+ /* board specific */
+ #include "acpi/mainboard.asl"
+}
diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
new file mode 100644
index 0000000..5bed2c1
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+int board_early_init_f(void)
+{
+ /*
+ * The FSP enables the BayTrail internal legacy UART (again).
+ * Disable it again, so that the one on the EC can be used.
+ */
+ setup_internal_uart(0);
+
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
+ return 0;
+}
diff --git a/board/advantech/som-db5800-som-6867/start.S b/board/advantech/som-db5800-som-6867/start.S
new file mode 100644
index 0000000..2c941a4
--- /dev/null
+++ b/board/advantech/som-db5800-som-6867/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ jmp early_board_init_ret
diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
index 6a946d5..737e610 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
+++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -12,6 +12,7 @@
int board_early_init_f(void)
{
+#ifndef CONFIG_INTERNAL_UART
/*
* The FSP enables the BayTrail internal legacy UART (again).
* Disable it again, so that the Winbond one can be used.
@@ -21,6 +22,7 @@ int board_early_init_f(void)
/* Enable the legacy UART in the Winbond W83627 Super IO chip */
winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
UART0_BASE, UART0_IRQ);
+#endif
return 0;
}