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authorAneesh Bansal <aneesh.bansal@freescale.com>2015-06-16 10:36:30 +0530
committerYork Sun <yorksun@freescale.com>2015-07-31 08:50:18 -0700
commit73cc2f50eb748475beb004cb37459f1b58e09a09 (patch)
tree027d97a08c6dfe33e7dcaceee0dbb5f4b20e0663 /board
parent467a40dfe35f48d830f01a72617207d03ca85b4d (diff)
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powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/corenet_ds/MAINTAINERS2
1 files changed, 2 insertions, 0 deletions
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 6855446..73b0553 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD
M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained
F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
+F: configs/P5020DS_NAND_SECURE_BOOT_defconfig
+F: configs/P5040DS_NAND_SECURE_BOOT_defconfig