diff options
| author | Dave Liu <r63238@freescale.com> | 2008-03-26 22:56:36 +0800 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-03-28 14:11:51 -0500 |
| commit | 6f8c85e8d1865730c158d9ef5a06c70c3a10600a (patch) | |
| tree | ef387eee13d4f4e4d196ea17ed794890e88df92f /board | |
| parent | 74d1e66d22dac91388bc538b2fe19f735edc5b82 (diff) | |
| download | u-boot-imx-6f8c85e8d1865730c158d9ef5a06c70c3a10600a.zip u-boot-imx-6f8c85e8d1865730c158d9ef5a06c70c3a10600a.tar.gz u-boot-imx-6f8c85e8d1865730c158d9ef5a06c70c3a10600a.tar.bz2 | |
mpc83xx: initialize serdes for MPC837xEMDS boards
This patch is stolen from Anton Vorontsov's patch
for mpc837xerdb boards.
The reference clk and xcorevdd voltage of serdes1/2
is same between mpc837xemds and mpc837xerdb.
8377E: LYNX1- 2 SATA LYNX2- 2 PCIE
8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE
8379E: LYNX1- 2 SATA LYNX2- 2 SATA
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mpc837xemds/mpc837xemds.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index e57a53f..6fbd0e0 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -12,6 +12,8 @@ #include <common.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> #include <spd_sdram.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> @@ -29,6 +31,37 @@ int board_early_init_f(void) /* Clear all of the interrupt of BCSR */ bcsr[0xe] = 0xff; +#ifdef CONFIG_FSL_SERDES + immap_t *immr = (immap_t *)CFG_IMMR; + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* we check only part num, and don't look for CPU revisions */ + switch (spridr >> 16) { + case SPR_8379E_REV10 >> 16: + case SPR_8379_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8378E_REV10 >> 16: + case SPR_8378_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8377E_REV10 >> 16: + case SPR_8377_REV10 >> 16: + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + default: + printf("serdes not configured: unknown CPU part number: " + "%04x\n", spridr >> 16); + break; + } +#endif /* CONFIG_FSL_SERDES */ return 0; } |