sbc8548: Fix LBC SDRAM initialization settings

These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size).  Set the values
by comparing to the register file for the board used during
JTAG init sequence:

	LSDMR1		0x2863B727	/* PCHALL */
	LSDMR2		0x0863B727	/* NORMAL */
	LSDMR3		0x1863B727	/* MRW    */
	LSDMR4		0x4063B727	/* RFEN   */

This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.

The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.

We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 16 insertions, 13 deletions

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 63d504d..96554b2 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -107,13 +107,14 @@ void lbc_sdram_init(void)
 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 
 	uint idx;
+	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-	uint lsdmr_common;
+	uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
 
 	puts("    SDRAM: ");
 
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size(size, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
@@ -131,47 +132,49 @@ void lbc_sdram_init(void)
 	asm("msync");
 
 	/*
-	 * MPC8548 uses "new" 15-16 style addressing.
-	 */
-	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
-	lsdmr_common |= LSDMR_BSMA1516;
-
-	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
+	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
+	*sdram_addr2 = 0xff;
+	ppcDcbf((unsigned long) sdram_addr2);
 	udelay(100);
 
 	/*
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
+		out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
+		*sdram_addr2 = 0xff;
+		ppcDcbf((unsigned long) sdram_addr2);
 		udelay(100);
 	}
 
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
+	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
+	*sdram_addr2 = 0xff;
+	ppcDcbf((unsigned long) sdram_addr2);
 	udelay(100);
 
 	/*
-	 * Issue NORMAL OP command.
+	 * Issue RFEN command.
 	 */
-	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
+	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
+	*sdram_addr2 = 0xff;
+	ppcDcbf((unsigned long) sdram_addr2);
 	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 
 #endif	/* enable SDRAM init */