cleanup: Fix typos and misspellings in various files.

Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address

Signed-off-by: Mike Williams <mike@mikebwilliams.com>

10 files changed, 10 insertions, 10 deletions

diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
index e4fefb3..6cae9ea 100644
--- a/board/Marvell/common/bootseq.txt
+++ b/board/Marvell/common/bootseq.txt
@@ -62,7 +62,7 @@ in_flash:
 	    remap gt regs?
 	    map PCI mem/io
 	    map device space
-	    clear out interupts
+	    clear out interrupts
 	init_timebase
 	env_init
 	serial_init
diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c
index 8d87b2d..d53495c 100644
--- a/board/Marvell/common/i2c.c
+++ b/board/Marvell/common/i2c.c
@@ -420,7 +420,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
 	status = i2c_get_data (data, len);
 	if (status) {
 #ifdef DEBUG_I2C
-		printf ("Data not recieved: 0x%02x\n", status);
+		printf ("Data not received: 0x%02x\n", status);
 #endif
 		return status;
 	}
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
index 0a2951b..9306381 100644
--- a/board/Marvell/common/ns16550.h
+++ b/board/Marvell/common/ns16550.h
@@ -51,7 +51,7 @@ struct NS16550
 #define dlm ier
 
 #define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*reciever soft reset*/
+#define FCR_RXSR        0x02    /*receiver soft reset*/
 #define FCR_TXSR        0x04    /*transmitter soft reset*/
 
 
diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h
index 5e4f076..03fcd88 100644
--- a/board/Marvell/include/mv_gen_reg.h
+++ b/board/Marvell/include/mv_gen_reg.h
@@ -2237,7 +2237,7 @@
 #define CHANNEL2_REGISTER10				    0x9070
 #define CHANNEL2_REGISTER11				    0x9074
 
-/* MPSCs Interupts  */
+/* MPSCs Interrupts  */
 
 #define MPSC0_CAUSE						0xb824
 #define MPSC0_MASK						0xb8a4
diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h
index 8aa251d..2087a4a 100644
--- a/board/bmw/ns16550.h
+++ b/board/bmw/ns16550.h
@@ -37,7 +37,7 @@ struct NS16550 {
 #define afr iirfcrafr
 
 #define FCR_FIFO_EN     0x01	/*fifo enable */
-#define FCR_RXSR        0x02	/*reciever soft reset */
+#define FCR_RXSR        0x02	/*receiver soft reset */
 #define FCR_TXSR        0x04	/*transmitter soft reset */
 #define FCR_DMS		0x08	/* DMA Mode Select */
 
diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt
index e4fefb3..6cae9ea 100644
--- a/board/evb64260/bootseq.txt
+++ b/board/evb64260/bootseq.txt
@@ -62,7 +62,7 @@ in_flash:
 	    remap gt regs?
 	    map PCI mem/io
 	    map device space
-	    clear out interupts
+	    clear out interrupts
 	init_timebase
 	env_init
 	serial_init
diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c
index c62b647..88d0dac 100644
--- a/board/evb64260/i2c.c
+++ b/board/evb64260/i2c.c
@@ -306,7 +306,7 @@ i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data,
 	status = i2c_get_data(data, len);
 	if (status) {
 #ifdef DEBUG_I2C
-		printf("Data not recieved: 0x%02x\n", status);
+		printf("Data not received: 0x%02x\n", status);
 #endif
 		return status;
 	}
diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c
index 66acc41..2caf4aa 100644
--- a/board/freescale/mpc8266ads/mpc8266ads.c
+++ b/board/freescale/mpc8266ads/mpc8266ads.c
@@ -392,7 +392,7 @@ phys_size_t initdram(int board_type)
        The 11th column addre will still be mucxed correctly onto the bus.
 
        Also be aware that the MPC8266ADS board Rev B has not connected
-       Row addres 13 to anything.
+       Row address 13 to anything.
 
        The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
     */
diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h
index 39e0378..fd11555 100644
--- a/board/intercontrol/digsy_mtc/eeprom.h
+++ b/board/intercontrol/digsy_mtc/eeprom.h
@@ -27,6 +27,6 @@
 #define EEPROM_ADDR_IDENT	0	/* identification word offset */
 #define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
 #define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
-#define EEPROM_ADDR_ETHADDR	23	/* ethernet addres offset */
+#define EEPROM_ADDR_ETHADDR	23	/* ethernet address offset */
 
 #endif
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
index a009437..89d2e0a 100644
--- a/board/mpl/common/usb_uhci.c
+++ b/board/mpl/common/usb_uhci.c
@@ -67,7 +67,7 @@
  *
  * Interrupt Transfers.
  * --------------------
- * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
  * will be inserted after the appropriate (depending the interval setting) skeleton TD.
  * If an interrupt has been detected the dev->irqhandler is called. The status and number
  * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the