Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  arm, davinci: add DAVINCI_MMC_CLKID
  arm, davinci_emac: fix driver bug if more then 3 PHYs are detected
  arm, davinci: da850/dm365 lowlevel cleanup
  omap5: Add omap5_evm board build support.
  omap4/5: Add support for booting with CH.
  omap5: emif: Add emif/ddr configurations required for omap5 evm
  omap5: clocks: Add clocks support for omap5 platform.
  omap5: Add minimal support for omap5430.
  omap: Checkpatch fixes
  omap4: make omap4 code common for future reuse
  GCC4.6: Squash warnings in onenand_base.c
  GCC4.6: Fix common/usb.c on xscale
  OneNAND: Add simple OneNAND SPL
  PXA: vpac270: Enable the new generic MMC driver
  PXA: Cleanup serial_pxa
  PXA: Drop csb226 and innokom boards (unmaintained)
  m28evk: Fix comment about the number of RAM banks
  mx31: Fix checkpatch warnings in generic.c
  mx31: Use proper IO accessor for GPR register
  mx31: Remove duplicate definition for GPR register
  qong: Use generic function for configuring GPR register
  M28EVK: Enable USB HOST support
  iMX28: Add USB HOST driver
  iMX28: Add USB and USB PHY register definitions
  M28: Add memory detection into SPL
  iMX28: Fix ARM vector handling
  M28: Add doc/README.m28 documentation
  M28: Add MMC SPL
  iMX28: Add support for DENX M28EVK board
  iMX28: Add u-boot.sb target to Makefile
  iMX28: Add image header generator tool
  iMX28: Add driver for internal RTC
  iMX28: Add GPMI NAND driver
  iMX28: Add APBH DMA driver
  iMX28: Add SPI driver
  iMX28: Add GPIO control
  iMX28: Add I2C bus driver
  iMX28: Add PINMUX control
  FEC: Add support for iMX28 quirks
  iMX28: Add SSP MMC driver
  iMX28: Initial support for iMX28 CPU
  MX25: zmx25: GCC4.6 fix build warnings
  da850: add new config file for AM18xx
  BeagleBoard: config: Switch to ttyO2
  OMAP3: Change omap3_evm maintainer
  devkit8000: Fix NAND SPL on boards with 256MB NAND
  integrator: enable Vpp and disable flash protection
  integrator: add system controller header
  integrator: make flash writeable on boot
  integrator: use io-accessors for board init
  integrator: move text offset to config
  integrator: pass configs for core modules
  ARM: remove superfluous setting of arch_number in board specific code.
  SPL: Allow ARM926EJS to avoid compiling in the CPU support code
  integrator: do not test first part of the memory
  arm: a320: fix broken timer
  ARM: define CONFIG_MACH_TYPE for all ronetix boards
  dm646x: pass board revision info to kernel
  dm646x: add new configuration for dm6467T
  arm, davinci: Fix setting of the SDRAM configuration register
  arm, davinci: Remove the duplication of LPSC functions
  arm, davinci: Rename AM1808 lowlevel functions to DA850
  da8xxevm: fix build error
  ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE

34 files changed, 2815 insertions, 1183 deletions

diff --git a/board/armltd/integrator/arm-ebi.h b/board/armltd/integrator/arm-ebi.h
new file mode 100644
index 0000000..2d85e3f
--- /dev/null
+++ b/board/armltd/integrator/arm-ebi.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the External Bus Interface (EBI)
+ * found in the ARM Integrator AP and CP reference designs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_EBI_H
+#define __ARM_EBI_H
+
+#define EBI_BASE		0x12000000
+
+#define EBI_CSR0_REG		0x00 /* CS0 = Boot ROM */
+#define EBI_CSR1_REG		0x04 /* CS1 = Flash */
+#define EBI_CSR2_REG		0x08 /* CS2 = SSRAM */
+#define EBI_CSR3_REG		0x0C /* CS3 = Expansion memory */
+/*
+ * The four upper bits are the waitstates for each chip select
+ * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
+ */
+#define EBI_CSR_WAIT_MASK	0xF0
+/* Whether memory is synchronous or asynchronous */
+#define EBI_CSR_SYNC_MASK	0xF7
+#define EBI_CSR_ASYNC		0x00
+#define EBI_CSR_SYNC		0x08
+/* Whether memory is write enabled or not */
+#define EBI_CSR_WREN_MASK	0xFB
+#define EBI_CSR_WREN_DISABLE	0x00
+#define EBI_CSR_WREN_ENABLE	0x04
+/* Memory bit width for each chip select */
+#define EBI_CSR_MEMSIZE_MASK	0xFC
+#define EBI_CSR_MEMSIZE_8BIT	0x00
+#define EBI_CSR_MEMSIZE_16BIT	0x01
+#define EBI_CSR_MEMSIZE_32BIT	0x02
+
+/*
+ * The lock register need to be written with 0xa05f before anything in the
+ * EBI can be changed.
+ */
+#define EBI_LOCK_REG		0x20
+#define EBI_UNLOCK_MAGIC	0xA05F
+
+#endif
diff --git a/board/armltd/integrator/config.mk b/board/armltd/integrator/config.mk
deleted file mode 100644
index 8b57af1..0000000
--- a/board/armltd/integrator/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# image should be loaded at 0x01000000
-#
-
-CONFIG_SYS_TEXT_BASE = 0x01000000
diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h
new file mode 100644
index 0000000..279dc55
--- /dev/null
+++ b/board/armltd/integrator/integrator-sc.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the System Controller (SC) and
+ * the similar "CP Controller" found in the ARM Integrator/AP and
+ * Integrator/CP reference designs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_SC_H
+#define __ARM_SC_H
+
+#define SC_BASE			0x11000000
+
+/*
+ * The system controller registers
+ */
+#define SC_ID_OFFSET		0x00
+#define SC_OSC_OFFSET		0x04
+/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
+#define SC_OSC_DIVXY		(1 << 8)
+#define SC_CTRLS_OFFSET		0x08
+#define SC_CTRLC_OFFSET		0x0C
+/* Set bits by writing CTRLS, clear bits by writing CTRLC */
+#define SC_CTRL_SOFTRESET	(1 << 0)
+#define SC_CTRL_FLASHVPP	(1 << 1)
+#define SC_CTRL_FLASHWP		(1 << 2)
+#define SC_CTRL_UART1DTR	(1 << 4)
+#define SC_CTRL_UART1RTS	(1 << 5)
+#define SC_CTRL_UART0DTR	(1 << 6)
+#define SC_CTRL_UART0RTS	(1 << 7)
+#define SC_DEC_OFFSET		0x10
+#define SC_ARB_OFFSET		0x14
+#define SC_PCI_OFFSET		0x18
+#define SC_PCI_PCIEN		(1 << 0)
+#define SC_PCI_PCIBINT_CLR	(1 << 1)
+#define SC_LOCK_OFFSET		0x1C
+#define SC_LBFADDR_OFFSET	0x20
+#define SC_LBFCODE_OFFSET	0x24
+
+#define SC_ID (SC_BASE + SC_ID_OFFSET)
+#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
+#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
+#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
+#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
+#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
+#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
+#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
+#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
+#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
+
+/*
+ * The Integrator/CP as a smaller set of registers, at a different
+ * offset - probably not to disturb old software.
+ */
+
+#define CP_BASE			0xCB000000
+
+#define CP_IDFIELD_OFFSET	0x00
+#define CP_FLASHPROG_OFFSET	0x04
+#define CP_FLASHPROG_FLVPPEN	(1 << 0)
+#define CP_FLASHPROG_FLWREN	(1 << 1)
+#define CP_FLASHPROG_FLASHSIZE	(1 << 2)
+#define CP_FLASHPROG_EXTRABANK	(1 << 3)
+#define CP_INTREG_OFFSET	0x08
+#define CP_DECODE_OFFSET	0x0C
+
+#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
+#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
+#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
+#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
+
+#endif
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index c8d2bc7..a507c09 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -35,6 +35,9 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/io.h>
+#include "arm-ebi.h"
+#include "integrator-sc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,6 +58,8 @@ void show_boot_progress(int progress)
 
 int board_init (void)
 {
+	u32 val;
+
 	/* arch number of Integrator Board */
 #ifdef CONFIG_ARCH_CINTEGRATOR
 	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
@@ -72,6 +77,37 @@ extern void cm_remap(void);
 	cm_remap();	/* remaps writeable memory to 0x00000000 */
 #endif
 
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	/*
+	 * Flash protection on the Integrator/CP is in a simple register
+	 */
+	val = readl(CP_FLASHPROG);
+	val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
+	writel(val, CP_FLASHPROG);
+#else
+	/*
+	 * The Integrator/AP has some special protection mechanisms
+	 * for the external memories, first the External Bus Interface (EBI)
+	 * then the system controller (SC).
+	 *
+	 * The system comes up with the flash memory non-writable and
+	 * configuration locked. If we want U-Boot to be used for flash
+	 * access we cannot have the flash memory locked.
+	 */
+	writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
+	val = readl(EBI_BASE + EBI_CSR1_REG);
+	val &= EBI_CSR_WREN_MASK;
+	val |= EBI_CSR_WREN_ENABLE;
+	writel(val, EBI_BASE + EBI_CSR1_REG);
+	writel(0, EBI_BASE + EBI_LOCK_REG);
+
+	/*
+	 * Set up the system controller to remove write protection from
+	 * the flash memory and enable Vpp
+	 */
+	writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
+#endif
+
 	icache_enable ();
 
 	return 0;
@@ -86,21 +122,30 @@ int misc_init_r (void)
 	return (0);
 }
 
+/*
+ * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
+ * from there, which means we cannot test the RAM underneath the ROM at this
+ * point. It will be unmapped later on, when we are executing from the
+ * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
+ * RAM on higher addresses works fine.
+ */
+#define REMAPPED_FLASH_SZ 0x40000
+
 int dram_init (void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 #ifdef CONFIG_CM_SPD_DETECT
 	{
 extern void dram_query(void);
-	unsigned long cm_reg_sdram;
-	unsigned long sdram_shift;
+	u32 cm_reg_sdram;
+	u32 sdram_shift;
 
 	dram_query();	/* Assembler accesses to CM registers */
 			/* Queries the SPD values	      */
 
 	/* Obtain the SDRAM size from the CM SDRAM register */
 
-	cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+	cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
 	/*   Register	      SDRAM size
 	 *
 	 *   0xXXXXXXbbb000bb	 16 MB
@@ -110,16 +155,18 @@ extern void dram_query(void);
 	 *   0xXXXXXXbbb100bb	256 MB
 	 *
 	 */
-	sdram_shift		 = ((cm_reg_sdram & 0x0000001C)/4)%4;
-	gd->bd->bi_dram[0].size	 = 0x01000000 << sdram_shift;
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+				    REMAPPED_FLASH_SZ,
 				    0x01000000 << sdram_shift);
 	}
 #else
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+				    REMAPPED_FLASH_SZ,
 				    PHYS_SDRAM_1_SIZE);
 #endif /* CM_SPD_DETECT */
+	/* We only have one bank of RAM, set it to whatever was detected */
+	gd->bd->bi_dram[0].size	 = gd->ram_size;
 
 	return 0;
 }
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
deleted file mode 100644
index dd29e62..0000000
--- a/board/csb226/csb226.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
- * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
- * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-/**
- * misc_init_r: - misc initialisation routines
- */
-
-int misc_init_r(void)
-{
-#if 0
-	uchar *str;
-
-	/* determine if the software update key is pressed during startup */
-	/* not ported yet... */
-	if (GPLR0 & 0x00000800) {
-		printf("using bootcmd_normal (sw-update button not pressed)\n");
-		str = getenv("bootcmd_normal");
-	} else {
-		printf("using bootcmd_update (sw-update button pressed)\n");
-		str = getenv("bootcmd_update");
-	}
-
-	setenv("bootcmd",str);
-#endif
-	return 0;
-}
-
-
-/**
- * board_init: - setup some data structures
- *
- * @return: 0 in case of success
- */
-
-int board_init (void)
-{
-	/* We have RAM, disable cache */
-	dcache_disable();
-	icache_disable();
-
-	/* arch number of CSB226 board */
-	gd->bd->bi_arch_number = MACH_TYPE_CSB226;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0xa0000100;
-
-	return 0;
-}
-
-
-extern void pxa_dram_init(void);
-int dram_init(void)
-{
-	pxa_dram_init();
-	gd->ram_size = PHYS_SDRAM_1_SIZE;
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-/**
- * csb226_set_led: - switch LEDs on or off
- *
- * @param led:   LED to switch (0,1,2)
- * @param state: switch on (1) or off (0)
- */
-
-void csb226_set_led(int led, int state)
-{
-	switch(led) {
-
-		case 0: if (state==1) {
-				writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
-			} else if (state==0) {
-				writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
-			}
-			break;
-
-		case 1: if (state==1) {
-				writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
-			} else if (state==0) {
-				writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
-			}
-			break;
-
-		case 2: if (state==1) {
-				writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
-			} else if (state==0) {
-				writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
-			}
-			break;
-	}
-
-	return;
-}
-
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
-	switch(status) {
-		case  1: csb226_set_led(0,1); break;
-		case  5: csb226_set_led(1,1); break;
-		case 15: csb226_set_led(2,1); break;
-	}
-
-	return;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_CS8900
-	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/csb226/flash.c b/board/csb226/flash.c
deleted file mode 100644
index e103470..0000000
--- a/board/csb226/flash.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
- * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-
-#define FLASH_BANK_SIZE 0x02000000
-#define MAIN_SECT_SIZE	0x40000		/* 2x16 = 256k per sector */
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/**
- * flash_init: - initialize data structures for flash chips
- *
- * @return: size of the flash
- */
-
-ulong flash_init(void)
-{
-	int i, j;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		ulong flashbase = 0;
-		flash_info[i].flash_id =
-			(INTEL_MANUFACT & FLASH_VENDMASK) |
-			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
-		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-		switch (i) {
-		case 0:
-			flashbase = PHYS_FLASH_1;
-			break;
-		default:
-			panic("configured too many flash banks!\n");
-			break;
-		}
-		for (j = 0; j < flash_info[i].sector_count; j++) {
-			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors */
-	flash_protect(FLAG_PROTECT_SET,
-			CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-			&flash_info[0]);
-
-	flash_protect(FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR,
-			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-			&flash_info[0]);
-
-	return size;
-}
-
-
-/**
- * flash_print_info: - print information about the flash situation
- */
-
-void flash_print_info  (flash_info_t *info)
-{
-	int i, j;
-
-	for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
-
-		switch (info->flash_id & FLASH_VENDMASK) {
-		case (INTEL_MANUFACT & FLASH_VENDMASK):
-			printf ("Intel: ");
-			break;
-		default:
-			printf ("Unknown Vendor ");
-			break;
-		}
-
-		switch (info->flash_id & FLASH_TYPEMASK) {
-		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-			printf("28F128J3 (128Mbit)\n");
-			break;
-		default:
-			printf("Unknown Chip Type\n");
-			return;
-		}
-
-		printf("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-		printf("  Sector Start Addresses:");
-		for (i = 0; i < info->sector_count; i++) {
-			if ((i % 5) == 0) printf ("\n	");
-
-			printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "	   ");
-		}
-		printf ("\n");
-		info++;
-	}
-}
-
-
-/**
- * flash_erase: - erase flash sectors
- */
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	int rc = ERR_OK;
-	ulong start;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return ERR_UNKNOWN_FLASH_TYPE;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		return ERR_INVAL;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
-		return ERR_UNKNOWN_FLASH_VENDOR;
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) prot++;
-	}
-
-	if (prot) return ERR_PROTECTED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
-
-		printf("Erasing sector %2d ... ", sect);
-
-		/* arm simple, non interrupt dependent timer */
-		start = get_timer(0);
-
-		if (info->protect[sect] == 0) { /* not protected */
-			u32 * volatile addr = (u32 * volatile)(info->start[sect]);
-
-			/* erase sector:				    */
-			/* The strata flashs are aligned side by side on    */
-			/* the data bus, so we have to write the commands   */
-			/* to both chips here:				    */
-
-			*addr = 0x00200020;	/* erase setup */
-			*addr = 0x00D000D0;	/* erase confirm */
-
-			while ((*addr & 0x00800080) != 0x00800080) {
-				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					*addr = 0x00B000B0; /* suspend erase*/
-					*addr = 0x00FF00FF; /* read mode    */
-					rc = ERR_TIMOUT;
-					goto outahere;
-				}
-			}
-			*addr = 0x00500050; /* clear status register cmd.   */
-			*addr = 0x00FF00FF; /* reset to read mode	    */
-		}
-		printf("ok.\n");
-	}
-	if (ctrlc()) printf("User Interrupt!\n");
-
-outahere:
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked(10000);
-
-	if (flag) enable_interrupts();
-
-	return rc;
-}
-
-/**
- * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
- */
-
-static int write_long (flash_info_t *info, ulong dest, ulong data)
-{
-	u32 * volatile addr = (u32 * volatile)dest, val;
-	int rc = ERR_OK;
-	int flag;
-	ulong start;
-
-	/* read array command - just for the case... */
-	*addr = 0x00FF00FF;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) return ERR_NOT_ERASED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	flag = disable_interrupts();
-
-	/* clear status register command */
-	*addr = 0x00500050;
-
-	/* program set-up command */
-	*addr = 0x00400040;
-
-	/* latch address/data */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait while polling the status register */
-	while(((val = *addr) & 0x00800080) != 0x00800080) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = ERR_TIMOUT;
-			/* suspend program command */
-			*addr = 0x00B000B0;
-			goto outahere;
-		}
-	}
-
-	/* check for errors */
-	if(val & 0x001A001A) {
-		printf("\nFlash write error %02x at address %08lx\n",
-			(int)val, (unsigned long)dest);
-		if(val & 0x00080008) {
-			printf("Voltage range error.\n");
-			rc = ERR_PROG_ERROR;
-			goto outahere;
-		}
-		if(val & 0x00020002) {
-			printf("Device protect error.\n");
-			rc = ERR_PROTECTED;
-			goto outahere;
-		}
-		if(val & 0x00100010) {
-			printf("Programming error.\n");
-			rc = ERR_PROG_ERROR;
-			goto outahere;
-		}
-		rc = ERR_PROG_ERROR;
-		goto outahere;
-	}
-
-outahere:
-	/* read array command */
-	*addr = 0x00FF00FF;
-	if (flag) enable_interrupts();
-
-	return rc;
-}
-
-
-/**
- * write_buf: - Copy memory to flash.
- *
- * @param info:
- * @param src:	source of copy transaction
- * @param addr: where to copy to
- * @param cnt:	number of bytes to copy
- *
- * @return	error code
- */
-
-/* "long" version, uses 32bit words */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	ulong data;
-	int l;
-	int i, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 24);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data >> 8) | (*src++ << 24);
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 24);
-		}
-
-		if ((rc = write_long(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = *((ulong*)src);
-		if ((rc = write_long(info, wp, data)) != 0) {
-			return (rc);
-		}
-		src += 4;
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) return ERR_OK;
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 24);
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *)cp << 24);
-	}
-
-	return write_long(info, wp, data);
-}
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 665aedf..c41f11d 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -231,7 +231,7 @@ static void board_nand_setup(void)
 
 	mxc_setup_weimcs(3, &cs3);
 
-	__REG(IOMUXC_GPR) |= 1 << 13;
+	mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
 
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
index 1a01c3c..ac82d5c 100644
--- a/board/davinci/dm6467evm/dm6467evm.c
+++ b/board/davinci/dm6467evm/dm6467evm.c
@@ -24,6 +24,26 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define REV_DM6467EVM		0
+#define REV_DM6467TEVM		1
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3]	System clock frequency
+ * 0000b	- 27 MHz
+ * 0001b	- 33 MHz
+ */
+u32 get_board_rev(void)
+{
+
+#ifdef DAVINCI_DM6467TEVM
+	return REV_DM6467TEVM;
+#else
+	return REV_DM6467EVM;
+#endif
+
+}
+
 int board_init(void)
 {
 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
diff --git a/board/csb226/Makefile b/board/denx/m28evk/Makefile
index 6fe9bec..b6f002f 100644
--- a/board/csb226/Makefile
+++ b/board/denx/m28evk/Makefile
@@ -25,7 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= csb226.o flash.o
+ifndef	CONFIG_SPL_BUILD
+COBJS	:= m28evk.o
+endif
+
+ifdef	CONFIG_SPL_BUILD
+COBJS	:= mem_init.o mmc_boot.o power_init.o memsize.o
+endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -33,6 +39,13 @@ OBJS	:= $(addprefix $(obj),$(COBJS))
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+all:	$(ALL)
+
+ifdef	CONFIG_SPL_BUILD
+memsize.c:
+	ln -sf $(TOPDIR)/common/memsize.c $@
+endif
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/board/denx/m28evk/m28_init.h b/board/denx/m28evk/m28_init.h
new file mode 100644
index 0000000..98d3631
--- /dev/null
+++ b/board/denx/m28evk/m28_init.h
@@ -0,0 +1,41 @@
+/*
+ * Freescale i.MX28 SPL functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__M28_INIT_H__
+#define	__M28_INIT_H__
+
+void early_delay(int delay);
+
+void mx28_power_init(void);
+
+#ifdef	CONFIG_SPL_MX28_PSWITCH_WAIT
+void mx28_power_wait_pswitch(void);
+#else
+static inline void mx28_power_wait_pswitch(void) { }
+#endif
+
+void mx28_mem_init(void);
+
+#endif	/* __M28_INIT_H__ */
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
new file mode 100644
index 0000000..8cf3dc9
--- /dev/null
+++ b/board/denx/m28evk/m28evk.c
@@ -0,0 +1,216 @@
+/*
+ * DENX M28 module
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mx28_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	/* SSP2 clock at 96MHz */
+	mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+#ifdef	CONFIG_CMD_USB
+	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
+	mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
+			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
+	gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#define	HW_DIGCTRL_SCRATCH0	0x8001c280
+#define	HW_DIGCTRL_SCRATCH1	0x8001c290
+int dram_init(void)
+{
+	uint32_t sz[2];
+
+	sz[0] = readl(HW_DIGCTRL_SCRATCH0);
+	sz[1] = readl(HW_DIGCTRL_SCRATCH1);
+
+	if (sz[0] != sz[1]) {
+		printf("MX28:\n"
+			"Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
+			"HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
+			"verify these two registers contain valid RAM size!\n");
+		hang();
+	}
+
+	gd->ram_size = sz[0];
+	return 0;
+}
+
+#ifdef	CONFIG_CMD_MMC
+static int m28_mmc_wp(int id)
+{
+	if (id != 0) {
+		printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+		return 1;
+	}
+
+	return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Configure WP as output */
+	gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+
+	return mxsmmc_initialize(bis, 0, m28_mmc_wp);
+}
+#endif
+
+#ifdef	CONFIG_CMD_NET
+
+#define	MII_OPMODE_STRAP_OVERRIDE	0x16
+#define	MII_PHY_CTRL1			0x1e
+#define	MII_PHY_CTRL2			0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+	miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+	miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+	if (phy == 3)
+		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct mx28_clkctrl_regs *clkctrl_regs =
+		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+
+	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+	if (ret) {
+		printf("FEC MXS: Unable to init FEC0\n");
+		return ret;
+	}
+
+	ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+	if (ret) {
+		printf("FEC MXS: Unable to init FEC1\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC0");
+	if (!dev) {
+		printf("FEC MXS: Unable to get FEC0 device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		printf("FEC MXS: Unable to register FEC0 mii postcall\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC1");
+	if (!dev) {
+		printf("FEC MXS: Unable to get FEC1 device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		printf("FEC MXS: Unable to register FEC1 mii postcall\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+#ifdef	CONFIG_M28_FEC_MAC_IN_OCOTP
+
+#define	MXS_OCOTP_MAX_TIMEOUT	1000000
+void imx_get_mac_from_fuse(char *mac)
+{
+	struct mx28_ocotp_regs *ocotp_regs =
+		(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+	uint32_t data;
+
+	memset(mac, 0, 6);
+
+	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+	if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+				MXS_OCOTP_MAX_TIMEOUT)) {
+		printf("MXS FEC: Can't get MAC from OCOTP\n");
+		return;
+	}
+
+	data = readl(&ocotp_regs->hw_ocotp_cust0);
+
+	mac[0] = 0x00;
+	mac[1] = 0x04;
+	mac[2] = (data >> 24) & 0xff;
+	mac[3] = (data >> 16) & 0xff;
+	mac[4] = (data >> 8) & 0xff;
+	mac[5] = data & 0xff;
+}
+#else
+void imx_get_mac_from_fuse(char *mac)
+{
+	memset(mac, 0, 6);
+}
+#endif
+
+#endif
diff --git a/board/denx/m28evk/mem_init.c b/board/denx/m28evk/mem_init.c
new file mode 100644
index 0000000..17d1f9b
--- /dev/null
+++ b/board/denx/m28evk/mem_init.c
@@ -0,0 +1,240 @@
+/*
+ * Freescale i.MX28 RAM init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+
+#include "m28_init.h"
+
+uint32_t dram_vals[] = {
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
+	0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
+	0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
+	0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
+	0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
+	0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
+	0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
+	0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
+	0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
+	0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+	0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+};
+
+void init_m28_200mhz_ddr2(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+
+void mx28_mem_init_clock(void)
+{
+	struct mx28_clkctrl_regs *clkctrl_regs =
+		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	/* Gate EMI clock */
+	writel(CLKCTRL_FRAC0_CLKGATEEMI,
+		&clkctrl_regs->hw_clkctrl_frac0_set);
+
+	/* EMI = 205MHz */
+	writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
+		&clkctrl_regs->hw_clkctrl_frac0_set);
+	writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
+		CLKCTRL_FRAC0_EMIFRAC_MASK,
+		&clkctrl_regs->hw_clkctrl_frac0_clr);
+
+	/* Ungate EMI clock */
+	writel(CLKCTRL_FRAC0_CLKGATEEMI,
+		&clkctrl_regs->hw_clkctrl_frac0_clr);
+
+	early_delay(11000);
+
+	writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
+		(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
+		&clkctrl_regs->hw_clkctrl_emi);
+
+	/* Unbypass EMI */
+	writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
+		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+	early_delay(10000);
+}
+
+void mx28_mem_setup_cpu_and_hbus(void)
+{
+	struct mx28_clkctrl_regs *clkctrl_regs =
+		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	/* CPU = 454MHz and ungate CPU clock */
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
+		CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
+		19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+
+	/* Set CPU bypass */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+		&clkctrl_regs->hw_clkctrl_clkseq_set);
+
+	/* HBUS = 151MHz */
+	writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
+	writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
+		&clkctrl_regs->hw_clkctrl_hbus_clr);
+
+	early_delay(10000);
+
+	/* CPU clock divider = 1 */
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
+			CLKCTRL_CPU_DIV_CPU_MASK, 1);
+
+	/* Disable CPU bypass */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+void mx28_mem_setup_vdda(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
+		(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
+		POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
+		&power_regs->hw_power_vddactrl);
+}
+
+void mx28_mem_setup_vddd(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
+		(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
+		POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
+		&power_regs->hw_power_vdddctrl);
+}
+
+#define	HW_DIGCTRL_SCRATCH0	0x8001c280
+#define	HW_DIGCTRL_SCRATCH1	0x8001c290
+void data_abort_memdetect_handler(void) __attribute__((naked));
+void data_abort_memdetect_handler(void)
+{
+	asm volatile("subs pc, r14, #4");
+}
+
+void mx28_mem_get_size(void)
+{
+	uint32_t sz, da;
+	uint32_t *vt = (uint32_t *)0x20;
+
+	/* Replace the DABT handler. */
+	da = vt[4];
+	vt[4] = (uint32_t)&data_abort_memdetect_handler;
+
+	sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	writel(sz, HW_DIGCTRL_SCRATCH0);
+	writel(sz, HW_DIGCTRL_SCRATCH1);
+
+	/* Restore the old DABT handler. */
+	vt[4] = da;
+}
+
+void mx28_mem_init(void)
+{
+	struct mx28_clkctrl_regs *clkctrl_regs =
+		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct mx28_pinctrl_regs *pinctrl_regs =
+		(struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
+
+	/* Set DDR2 mode */
+	writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
+		&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
+
+	/* Power up PLL0 */
+	writel(CLKCTRL_PLL0CTRL0_POWER,
+		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+
+	early_delay(11000);
+
+	mx28_mem_init_clock();
+
+	mx28_mem_setup_vdda();
+
+	/*
+	 * Configure the DRAM registers
+	 */
+
+	/* Clear START bit from DRAM_CTL16 */
+	clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+	init_m28_200mhz_ddr2();
+
+	/* Clear SREFRESH bit from DRAM_CTL17 */
+	clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
+
+	/* Set START bit in DRAM_CTL16 */
+	setbits_le32(MXS_DRAM_BASE + 0x40, 1);
+
+	/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
+	while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
+		;
+
+	mx28_mem_setup_vddd();
+
+	early_delay(10000);
+
+	mx28_mem_setup_cpu_and_hbus();
+
+	mx28_mem_get_size();
+}
diff --git a/board/denx/m28evk/mmc_boot.c b/board/denx/m28evk/mmc_boot.c
new file mode 100644
index 0000000..86d3ab5
--- /dev/null
+++ b/board/denx/m28evk/mmc_boot.c
@@ -0,0 +1,273 @@
+/*
+ * Freescale i.MX28 Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+
+#include "m28_init.h"
+
+/*
+ * This delay function is intended to be used only in early stage of boot, where
+ * clock are not set up yet. The timer used here is reset on every boot and
+ * takes a few seconds to roll. The boot doesn't take that long, so to keep the
+ * code simple, it doesn't take rolling into consideration.
+ */
+#define	HW_DIGCTRL_MICROSECONDS	0x8001c0c0
+void early_delay(int delay)
+{
+	uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
+	st += delay;
+	while (st > readl(HW_DIGCTRL_MICROSECONDS))
+		;
+}
+
+#define	MUX_CONFIG_LED	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA)
+#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_GPMI	(MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* LED */
+	MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
+
+	/* framebuffer */
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+
+	/* UART1 */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+	MX28_PAD_AUART0_TX__DUART_RTS,
+	MX28_PAD_AUART0_RX__DUART_CTS,
+
+	/* UART2 */
+	MX28_PAD_AUART1_RX__AUART1_RX,
+	MX28_PAD_AUART1_TX__AUART1_TX,
+	MX28_PAD_AUART1_RTS__AUART1_RTS,
+	MX28_PAD_AUART1_CTS__AUART1_CTS,
+
+	/* CAN */
+	MX28_PAD_GPMI_RDY2__CAN0_TX,
+	MX28_PAD_GPMI_RDY3__CAN0_RX,
+
+	/* I2C */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* TSC2007 */
+	MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
+
+	/* MMC0 */
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+	MX28_PAD_SSP0_SCK__SSP0_SCK |
+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+	MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0,	/* Power .. FIXME */
+	MX28_PAD_AUART2_CTS__GPIO_3_10,	/* WP ... FIXME */
+
+	/* GPMI NAND */
+	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDN__GPMI_RDN |
+		(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+	/* FEC Ethernet */
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+	/* I2C */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* SPI2 (for flash) */
+	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_SS0__SSP2_D3 |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void board_init_ll(void)
+{
+	mxs_iomux_setup_multiple_pads(iomux_setup, ARRAY_SIZE(iomux_setup));
+	mx28_power_init();
+	mx28_mem_init();
+	mx28_power_wait_pswitch();
+}
+
+/* Support aparatus */
+inline void board_init_f(unsigned long bootflag)
+{
+	for (;;)
+		;
+}
+
+inline void board_init_r(gd_t *id, ulong dest_addr)
+{
+	for (;;)
+		;
+}
+
+inline int printf(const char *fmt, ...)
+{
+	return 0;
+}
+
+inline void __coloured_LED_init(void) {}
+inline void __red_LED_on(void) {}
+void coloured_LED_init(void)
+	__attribute__((weak, alias("__coloured_LED_init")));
+void red_LED_on(void)
+	__attribute__((weak, alias("__red_LED_on")));
+void hang(void) __attribute__ ((noreturn));
+void hang(void)
+{
+	for (;;)
+		;
+}
diff --git a/board/denx/m28evk/power_init.c b/board/denx/m28evk/power_init.c
new file mode 100644
index 0000000..27322b4
--- /dev/null
+++ b/board/denx/m28evk/power_init.c
@@ -0,0 +1,913 @@
+/*
+ * Freescale i.MX28 Boot PMIC init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#include "m28_init.h"
+
+void mx28_power_clock2xtal(void)
+{
+	struct mx28_clkctrl_regs *clkctrl_regs =
+		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	/* Set XTAL as CPU reference clock */
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+		&clkctrl_regs->hw_clkctrl_clkseq_set);
+}
+
+void mx28_power_clock2pll(void)
+{
+	struct mx28_clkctrl_regs *clkctrl_regs =
+		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+	writel(CLKCTRL_PLL0CTRL0_POWER,
+		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+	early_delay(100);
+	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+void mx28_power_clear_auto_restart(void)
+{
+	struct mx28_rtc_regs *rtc_regs =
+		(struct mx28_rtc_regs *)MXS_RTC_BASE;
+
+	writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
+	while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
+		;
+
+	writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
+	while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
+		;
+
+	/*
+	 * Due to the hardware design bug of mx28 EVK-A
+	 * we need to set the AUTO_RESTART bit.
+	 */
+	if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
+		return;
+
+	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+		;
+
+	setbits_le32(&rtc_regs->hw_rtc_persistent0,
+			RTC_PERSISTENT0_AUTO_RESTART);
+	writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
+	writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
+	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+		;
+	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
+		;
+}
+
+void mx28_power_set_linreg(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	/* Set linear regulator 25mV below switching converter */
+	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+			POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+			POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+	clrsetbits_le32(&power_regs->hw_power_vddactrl,
+			POWER_VDDACTRL_LINREG_OFFSET_MASK,
+			POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+	clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+			POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
+			POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
+}
+
+void mx28_power_setup_5v_detect(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	/* Start 5V detection */
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+			POWER_5VCTRL_VBUSVALID_TRSH_MASK,
+			POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
+			POWER_5VCTRL_PWRUP_VBUS_CMPS);
+}
+
+void mx28_src_power_init(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	/* Improve efficieny and reduce transient ripple */
+	writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
+		POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
+
+	clrsetbits_le32(&power_regs->hw_power_dclimits,
+			POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
+			0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
+
+	setbits_le32(&power_regs->hw_power_battmonitor,
+			POWER_BATTMONITOR_EN_BATADJ);
+
+	/* Increase the RCSCALE level for quick DCDC response to dynamic load */
+	clrsetbits_le32(&power_regs->hw_power_loopctrl,
+			POWER_LOOPCTRL_EN_RCSCALE_MASK,
+			POWER_LOOPCTRL_RCSCALE_THRESH |
+			POWER_LOOPCTRL_EN_RCSCALE_8X);
+
+	clrsetbits_le32(&power_regs->hw_power_minpwr,
+			POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
+
+	/* 5V to battery handoff ... FIXME */
+	setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+	early_delay(30);
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+}
+
+void mx28_power_init_4p2_params(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	/* Setup 4P2 parameters */
+	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+		POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
+		POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_HEADROOM_ADJ_MASK,
+		0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
+
+	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+		POWER_DCDC4P2_DROPOUT_CTRL_MASK,
+		POWER_DCDC4P2_DROPOUT_CTRL_100MV |
+		POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+}
+
+void mx28_enable_4p2_dcdc_input(int xfer)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
+	uint32_t prev_5v_brnout, prev_5v_droop;
+
+	prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
+				POWER_5VCTRL_PWDN_5VBRNOUT;
+	prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
+				POWER_CTRL_ENIRQ_VDD5V_DROOP;
+
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+		&power_regs->hw_power_reset);
+
+	clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
+
+	if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_ENABLE_DCDC)) {
+		return;
+	}
+
+	/*
+	 * Recording orignal values that will be modified temporarlily
+	 * to handle a chip bug. See chip errata for CQ ENGR00115837
+	 */
+	tmp = readl(&power_regs->hw_power_5vctrl);
+	vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
+	vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
+
+	pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
+
+	/*
+	 * Disable mechanisms that get erroneously tripped by when setting
+	 * the DCDC4P2 EN_DCDC
+	 */
+	clrbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_VBUSVALID_5VDETECT |
+		POWER_5VCTRL_VBUSVALID_TRSH_MASK);
+
+	writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
+
+	if (xfer) {
+		setbits_le32(&power_regs->hw_power_5vctrl,
+				POWER_5VCTRL_DCDC_XFER);
+		early_delay(20);
+		clrbits_le32(&power_regs->hw_power_5vctrl,
+				POWER_5VCTRL_DCDC_XFER);
+
+		setbits_le32(&power_regs->hw_power_5vctrl,
+				POWER_5VCTRL_ENABLE_DCDC);
+	} else {
+		setbits_le32(&power_regs->hw_power_dcdc4p2,
+				POWER_DCDC4P2_ENABLE_DCDC);
+	}
+
+	early_delay(25);
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+			POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
+
+	if (vbus_5vdetect)
+		writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
+
+	if (!pwd_bo)
+		clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
+
+	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
+		clrbits_le32(&power_regs->hw_power_ctrl,
+				POWER_CTRL_VBUS_VALID_IRQ);
+
+	if (prev_5v_brnout) {
+		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+			&power_regs->hw_power_5vctrl_set);
+		writel(POWER_RESET_UNLOCK_KEY,
+			&power_regs->hw_power_reset);
+	} else {
+		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+			&power_regs->hw_power_5vctrl_clr);
+		writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+			&power_regs->hw_power_reset);
+	}
+
+	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
+		clrbits_le32(&power_regs->hw_power_ctrl,
+				POWER_CTRL_VDD5V_DROOP_IRQ);
+
+	if (prev_5v_droop)
+		clrbits_le32(&power_regs->hw_power_ctrl,
+				POWER_CTRL_ENIRQ_VDD5V_DROOP);
+	else
+		setbits_le32(&power_regs->hw_power_ctrl,
+				POWER_CTRL_ENIRQ_VDD5V_DROOP);
+}
+
+void mx28_power_init_4p2_regulator(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp, tmp2;
+
+	setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
+
+	writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
+
+	writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
+
+	/* Power up the 4p2 rail and logic/control */
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	/*
+	 * Start charging up the 4p2 capacitor. We ramp of this charge
+	 * gradually to avoid large inrush current from the 5V cable which can
+	 * cause transients/problems
+	 */
+	mx28_enable_4p2_dcdc_input(0);
+
+	if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+		/*
+		 * If we arrived here, we were unable to recover from mx23 chip
+		 * errata 5837. 4P2 is disabled and sufficient battery power is
+		 * not present. Exiting to not enable DCDC power during 5V
+		 * connected state.
+		 */
+		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_ENABLE_DCDC);
+		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+			&power_regs->hw_power_5vctrl_set);
+		hang();
+	}
+
+	/*
+	 * Here we set the 4p2 brownout level to something very close to 4.2V.
+	 * We then check the brownout status. If the brownout status is false,
+	 * the voltage is already close to the target voltage of 4.2V so we
+	 * can go ahead and set the 4P2 current limit to our max target limit.
+	 * If the brownout status is true, we need to ramp us the current limit
+	 * so that we don't cause large inrush current issues. We step up the
+	 * current limit until the brownout status is false or until we've
+	 * reached our maximum defined 4p2 current limit.
+	 */
+	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_BO_MASK,
+			22 << POWER_DCDC4P2_BO_OFFSET);	/* 4.15V */
+
+	if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
+		setbits_le32(&power_regs->hw_power_5vctrl,
+			0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+	} else {
+		tmp = (readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
+			POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+		while (tmp < 0x3f) {
+			if (!(readl(&power_regs->hw_power_sts) &
+					POWER_STS_DCDC_4P2_BO)) {
+				tmp = readl(&power_regs->hw_power_5vctrl);
+				tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+				early_delay(100);
+				writel(tmp, &power_regs->hw_power_5vctrl);
+				break;
+			} else {
+				tmp++;
+				tmp2 = readl(&power_regs->hw_power_5vctrl);
+				tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+				tmp2 |= tmp <<
+					POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+				writel(tmp2, &power_regs->hw_power_5vctrl);
+				early_delay(100);
+			}
+		}
+	}
+
+	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+}
+
+void mx28_power_init_dcdc_4p2_source(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	if (!(readl(&power_regs->hw_power_dcdc4p2) &
+		POWER_DCDC4P2_ENABLE_DCDC)) {
+		hang();
+	}
+
+	mx28_enable_4p2_dcdc_input(1);
+
+	if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_ENABLE_DCDC);
+		writel(POWER_5VCTRL_ENABLE_DCDC,
+			&power_regs->hw_power_5vctrl_clr);
+		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+			&power_regs->hw_power_5vctrl_set);
+	}
+}
+
+void mx28_power_enable_4p2(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t vdddctrl, vddactrl, vddioctrl;
+	uint32_t tmp;
+
+	vdddctrl = readl(&power_regs->hw_power_vdddctrl);
+	vddactrl = readl(&power_regs->hw_power_vddactrl);
+	vddioctrl = readl(&power_regs->hw_power_vddioctrl);
+
+	setbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+		POWER_VDDDCTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddactrl,
+		POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+		POWER_VDDACTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddioctrl,
+		POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
+
+	mx28_power_init_4p2_params();
+	mx28_power_init_4p2_regulator();
+
+	/* Shutdown battery (none present) */
+	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
+	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+	writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+
+	mx28_power_init_dcdc_4p2_source();
+
+	writel(vdddctrl, &power_regs->hw_power_vdddctrl);
+	early_delay(20);
+	writel(vddactrl, &power_regs->hw_power_vddactrl);
+	early_delay(20);
+	writel(vddioctrl, &power_regs->hw_power_vddioctrl);
+
+	/*
+	 * Check if FET is enabled on either powerout and if so,
+	 * disable load.
+	 */
+	tmp = 0;
+	tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
+			POWER_VDDDCTRL_DISABLE_FET);
+	tmp |= !(readl(&power_regs->hw_power_vddactrl) &
+			POWER_VDDACTRL_DISABLE_FET);
+	tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
+			POWER_VDDIOCTRL_DISABLE_FET);
+	if (tmp)
+		writel(POWER_CHARGE_ENABLE_LOAD,
+			&power_regs->hw_power_charge_clr);
+}
+
+void mx28_boot_valid_5v(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	/*
+	 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
+	 * disconnect event. FIXME
+	 */
+	writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
+		&power_regs->hw_power_5vctrl_set);
+
+	/* Configure polarity to check for 5V disconnection. */
+	writel(POWER_CTRL_POLARITY_VBUSVALID |
+		POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
+		&power_regs->hw_power_ctrl_clr);
+
+	writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
+		&power_regs->hw_power_ctrl_clr);
+
+	mx28_power_enable_4p2();
+}
+
+void mx28_powerdown(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
+	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+		&power_regs->hw_power_reset);
+}
+
+void mx28_handle_5v_conflict(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp;
+
+	setbits_le32(&power_regs->hw_power_vddioctrl,
+			POWER_VDDIOCTRL_BO_OFFSET_MASK);
+
+	for (;;) {
+		tmp = readl(&power_regs->hw_power_sts);
+
+		if (tmp & POWER_STS_VDDIO_BO) {
+			mx28_powerdown();
+			break;
+		}
+
+		if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
+			mx28_boot_valid_5v();
+			break;
+		} else {
+			mx28_powerdown();
+			break;
+		}
+	}
+}
+
+int mx28_get_batt_volt(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+	volt *= 8;
+	return volt;
+}
+
+int mx28_is_batt_ready(void)
+{
+	return (mx28_get_batt_volt() >= 3600);
+}
+
+void mx28_5v_boot(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	/*
+	 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
+	 * but their implementation always returns 1 so we omit it here.
+	 */
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		mx28_boot_valid_5v();
+		return;
+	}
+
+	early_delay(1000);
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		mx28_boot_valid_5v();
+		return;
+	}
+
+	mx28_handle_5v_conflict();
+}
+
+void mx28_init_batt_bo(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	/* Brownout at 3V */
+	clrsetbits_le32(&power_regs->hw_power_battmonitor,
+		POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
+		15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+
+	writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+	writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+}
+
+void mx28_switch_vddd_to_dcdc_source(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_LINREG_OFFSET_MASK,
+		POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+
+	clrbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
+		POWER_VDDDCTRL_DISABLE_STEPPING);
+}
+
+int mx28_is_batt_good(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t volt;
+
+	volt = readl(&power_regs->hw_power_battmonitor);
+	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+	volt *= 8;
+
+	if ((volt >= 2400) && (volt <= 4300))
+		return 1;
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	clrsetbits_le32(&power_regs->hw_power_charge,
+		POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+		POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
+
+	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	early_delay(500000);
+
+	volt = readl(&power_regs->hw_power_battmonitor);
+	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+	volt *= 8;
+
+	if (volt >= 3500)
+		return 0;
+
+	if (volt >= 2400)
+		return 1;
+
+	writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+		&power_regs->hw_power_charge_clr);
+	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+	return 0;
+}
+
+void mx28_power_configure_power_source(void)
+{
+	mx28_src_power_init();
+
+	mx28_5v_boot();
+	mx28_power_clock2pll();
+
+	mx28_init_batt_bo();
+	mx28_switch_vddd_to_dcdc_source();
+}
+
+void mx28_enable_output_rail_protection(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+		POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+	setbits_le32(&power_regs->hw_power_vdddctrl,
+			POWER_VDDDCTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddactrl,
+			POWER_VDDACTRL_PWDN_BRNOUT);
+
+	setbits_le32(&power_regs->hw_power_vddioctrl,
+			POWER_VDDIOCTRL_PWDN_BRNOUT);
+}
+
+int mx28_get_vddio_power_source_off(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp;
+
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		tmp = readl(&power_regs->hw_power_vddioctrl);
+		if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
+			if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+				POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+				return 1;
+			}
+		}
+
+		if (!(readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_ENABLE_DCDC)) {
+			if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+				POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+				return 1;
+			}
+		}
+	}
+
+	return 0;
+
+}
+
+int mx28_get_vddd_power_source_off(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t tmp;
+
+	tmp = readl(&power_regs->hw_power_vdddctrl);
+	if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
+		if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+			POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+			return 1;
+		}
+	}
+
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		if (!(readl(&power_regs->hw_power_5vctrl) &
+			POWER_5VCTRL_ENABLE_DCDC)) {
+			return 1;
+		}
+	}
+
+	if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
+		if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
+			POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t cur_target, diff, bo_int = 0;
+	uint32_t powered_by_linreg = 0;
+
+	new_brownout = new_target - new_brownout;
+
+	cur_target = readl(&power_regs->hw_power_vddioctrl);
+	cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+	cur_target *= 50;	/* 50 mV step*/
+	cur_target += 2800;	/* 2800 mV lowest */
+
+	powered_by_linreg = mx28_get_vddio_power_source_off();
+	if (new_target > cur_target) {
+
+		if (powered_by_linreg) {
+			bo_int = readl(&power_regs->hw_power_vddioctrl);
+			clrbits_le32(&power_regs->hw_power_vddioctrl,
+					POWER_CTRL_ENIRQ_VDDIO_BO);
+		}
+
+		setbits_le32(&power_regs->hw_power_vddioctrl,
+				POWER_VDDIOCTRL_BO_OFFSET_MASK);
+		do {
+			if (new_target - cur_target > 100)
+				diff = cur_target + 100;
+			else
+				diff = new_target;
+
+			diff -= 2800;
+			diff /= 50;
+
+			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+				POWER_VDDIOCTRL_TRG_MASK, diff);
+
+			if (powered_by_linreg)
+				early_delay(1500);
+			else {
+				while (!(readl(&power_regs->hw_power_sts) &
+					POWER_STS_DC_OK))
+					;
+
+			}
+
+			cur_target = readl(&power_regs->hw_power_vddioctrl);
+			cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+			cur_target *= 50;	/* 50 mV step*/
+			cur_target += 2800;	/* 2800 mV lowest */
+		} while (new_target > cur_target);
+
+		if (powered_by_linreg) {
+			writel(POWER_CTRL_VDDIO_BO_IRQ,
+				&power_regs->hw_power_ctrl_clr);
+			if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
+				setbits_le32(&power_regs->hw_power_vddioctrl,
+						POWER_CTRL_ENIRQ_VDDIO_BO);
+		}
+	} else {
+		do {
+			if (cur_target - new_target > 100)
+				diff = cur_target - 100;
+			else
+				diff = new_target;
+
+			diff -= 2800;
+			diff /= 50;
+
+			clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+				POWER_VDDIOCTRL_TRG_MASK, diff);
+
+			if (powered_by_linreg)
+				early_delay(1500);
+			else {
+				while (!(readl(&power_regs->hw_power_sts) &
+					POWER_STS_DC_OK))
+					;
+
+			}
+
+			cur_target = readl(&power_regs->hw_power_vddioctrl);
+			cur_target &= POWER_VDDIOCTRL_TRG_MASK;
+			cur_target *= 50;	/* 50 mV step*/
+			cur_target += 2800;	/* 2800 mV lowest */
+		} while (new_target < cur_target);
+	}
+
+	clrsetbits_le32(&power_regs->hw_power_vddioctrl,
+			POWER_VDDDCTRL_BO_OFFSET_MASK,
+			new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+}
+
+void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t cur_target, diff, bo_int = 0;
+	uint32_t powered_by_linreg = 0;
+
+	new_brownout = new_target - new_brownout;
+
+	cur_target = readl(&power_regs->hw_power_vdddctrl);
+	cur_target &= POWER_VDDDCTRL_TRG_MASK;
+	cur_target *= 25;	/* 25 mV step*/
+	cur_target += 800;	/* 800 mV lowest */
+
+	powered_by_linreg = mx28_get_vddd_power_source_off();
+	if (new_target > cur_target) {
+		if (powered_by_linreg) {
+			bo_int = readl(&power_regs->hw_power_vdddctrl);
+			clrbits_le32(&power_regs->hw_power_vdddctrl,
+					POWER_CTRL_ENIRQ_VDDD_BO);
+		}
+
+		setbits_le32(&power_regs->hw_power_vdddctrl,
+				POWER_VDDDCTRL_BO_OFFSET_MASK);
+
+		do {
+			if (new_target - cur_target > 100)
+				diff = cur_target + 100;
+			else
+				diff = new_target;
+
+			diff -= 800;
+			diff /= 25;
+
+			clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+				POWER_VDDDCTRL_TRG_MASK, diff);
+
+			if (powered_by_linreg)
+				early_delay(1500);
+			else {
+				while (!(readl(&power_regs->hw_power_sts) &
+					POWER_STS_DC_OK))
+					;
+
+			}
+
+			cur_target = readl(&power_regs->hw_power_vdddctrl);
+			cur_target &= POWER_VDDDCTRL_TRG_MASK;
+			cur_target *= 25;	/* 25 mV step*/
+			cur_target += 800;	/* 800 mV lowest */
+		} while (new_target > cur_target);
+
+		if (powered_by_linreg) {
+			writel(POWER_CTRL_VDDD_BO_IRQ,
+				&power_regs->hw_power_ctrl_clr);
+			if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
+				setbits_le32(&power_regs->hw_power_vdddctrl,
+						POWER_CTRL_ENIRQ_VDDD_BO);
+		}
+	} else {
+		do {
+			if (cur_target - new_target > 100)
+				diff = cur_target - 100;
+			else
+				diff = new_target;
+
+			diff -= 800;
+			diff /= 25;
+
+			clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+					POWER_VDDDCTRL_TRG_MASK, diff);
+
+			if (powered_by_linreg)
+				early_delay(1500);
+			else {
+				while (!(readl(&power_regs->hw_power_sts) &
+					POWER_STS_DC_OK))
+					;
+
+			}
+
+			cur_target = readl(&power_regs->hw_power_vdddctrl);
+			cur_target &= POWER_VDDDCTRL_TRG_MASK;
+			cur_target *= 25;	/* 25 mV step*/
+			cur_target += 800;	/* 800 mV lowest */
+		} while (new_target < cur_target);
+	}
+
+	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
+			POWER_VDDDCTRL_BO_OFFSET_MASK,
+			new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+}
+
+void mx28_power_init(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	mx28_power_clock2xtal();
+	mx28_power_clear_auto_restart();
+	mx28_power_set_linreg();
+	mx28_power_setup_5v_detect();
+	mx28_power_configure_power_source();
+	mx28_enable_output_rail_protection();
+
+	mx28_power_set_vddio(3300, 3150);
+
+	mx28_power_set_vddd(1350, 1200);
+
+	writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
+		POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
+		POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
+		POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+
+	writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
+
+	early_delay(1000);
+}
+
+#ifdef	CONFIG_SPL_MX28_PSWITCH_WAIT
+void mx28_power_wait_pswitch(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
+		;
+}
+#endif
diff --git a/board/denx/m28evk/start.S b/board/denx/m28evk/start.S
new file mode 100644
index 0000000..94696d6
--- /dev/null
+++ b/board/denx/m28evk/start.S
@@ -0,0 +1,234 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Groger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Zupke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
+ *
+ * Change to support call back into iMX28 bootrom
+ * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#elif defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start:
+	b	reset
+	b	undefined_instruction
+	b	software_interrupt
+	b	prefetch_abort
+	b	data_abort
+	b	not_used
+	b	irq
+	b	fiq
+
+/*
+ * Vector table, located at address 0x20.
+ * This table allows the code running AFTER SPL, the U-Boot, to install it's
+ * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
+ * including it's interrupt vectoring table and the table at 0x0 is still the
+ * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
+ * is still used.
+ */
+_vt_reset:
+	.word	_reset
+_vt_undefined_instruction:
+	.word	_hang
+_vt_software_interrupt:
+	.word	_hang
+_vt_prefetch_abort:
+	.word	_hang
+_vt_data_abort:
+	.word	_hang
+_vt_not_used:
+	.word	_reset
+_vt_irq:
+	.word	_hang
+_vt_fiq:
+	.word	_hang
+
+reset:
+	ldr	pc, _vt_reset
+undefined_instruction:
+	ldr	pc, _vt_undefined_instruction
+software_interrupt:
+	ldr	pc, _vt_software_interrupt
+prefetch_abort:
+	ldr	pc, _vt_prefetch_abort
+data_abort:
+	ldr	pc, _vt_data_abort
+not_used:
+	ldr	pc, _vt_not_used
+irq:
+	ldr	pc, _vt_irq
+fiq:
+	ldr	pc, _vt_fiq
+
+	.balignl 16,0xdeadbeef
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+.globl _bss_start_ofs
+_bss_start_ofs:
+	.word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+	.word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
+	.word _end - _start
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+	.word	0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+_reset:
+	/*
+	 * Store all registers on old stack pointer, this will allow us later to
+	 * return to the BootROM and let the BootROM load U-Boot into RAM.
+	 */
+	push	{r0-r12,r14}
+
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+	bl	board_init_ll
+
+	pop	{r0-r12,r14}
+	bx	lr
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	mov	pc, lr		/* back to my caller */
+
+	.align	5
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+_hang:
+	ldr	sp, _TEXT_BASE			/* switch to abort stack */
+1:
+	bl	1b				/* hang and never return */
diff --git a/board/denx/m28evk/u-boot-spl.lds b/board/denx/m28evk/u-boot-spl.lds
new file mode 100644
index 0000000..e296a92
--- /dev/null
+++ b/board/denx/m28evk/u-boot-spl.lds
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	:
+	{
+		board/denx/m28evk/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	_end = .;
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	/DISCARD/ : { *(.bss*) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynsym*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.hash*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/board/denx/m28evk/u-boot.bd b/board/denx/m28evk/u-boot.bd
new file mode 100644
index 0000000..3ce7f92
--- /dev/null
+++ b/board/denx/m28evk/u-boot.bd
@@ -0,0 +1,14 @@
+sources {
+	u_boot_spl="spl/u-boot-spl.bin";
+	u_boot="u-boot.bin";
+}
+
+section (0) {
+        load u_boot_spl > 0x0000;
+        load ivt (entry = 0x0014) > 0x8000;
+	hab call 0x8000;
+
+        load u_boot > 0x40000100;
+        load ivt (entry = 0x40000100) > 0x8000;
+	hab call 0x8000;
+}
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
deleted file mode 100644
index ed4b987..0000000
--- a/board/innokom/flash.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
- *
- * (C) Copyright 2002
- * Auerswald GmbH & Co KG, Germany
- * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-
-/* Debugging macros ------------------------------------------------------  */
-
-#undef FLASH_DEBUG
-
-/* Some debug macros */
-#if (FLASH_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if FLASH_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef FLASH_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-/* ------------------------------------------------------------------------ */
-
-/* Development system: we have only 16 MB Flash                             */
-#ifdef CONFIG_MTD_INNOKOM_16MB
-#define FLASH_BANK_SIZE 0x01000000	/* 16 MB (during development)       */
-#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
-#endif
-
-/* Production system: we have 64 MB Flash                                   */
-#ifdef CONFIG_MTD_INNOKOM_64MB
-#define FLASH_BANK_SIZE 0x04000000	/* 64 MB                            */
-#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
-#endif
-
-flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/**
- * flash_init: - initialize data structures for flash chips
- *
- * @return: size of the flash
- */
-
-ulong flash_init(void)
-{
-	int i, j;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		ulong flashbase = 0;
-		flash_info[i].flash_id =
-			(INTEL_MANUFACT & FLASH_VENDMASK) |
-			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
-		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-
-		switch (i) {
-			case 0:
-				flashbase = PHYS_FLASH_1;
-				break;
-			default:
-				panic("configured too many flash banks!\n");
-				break;
-		}
-		for (j = 0; j < flash_info[i].sector_count; j++) {
-			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect u-boot sectors */
-	flash_protect(FLAG_PROTECT_SET,
-			CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_BASE + (256*1024) - 1,
-			&flash_info[0]);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	flash_protect(FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR,
-			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-			&flash_info[0]);
-#endif
-
-	return size;
-}
-
-
-/**
- * flash_print_info: - print information about the flash situation
- *
- * @param info:
- */
-
-void flash_print_info  (flash_info_t *info)
-{
-	int i, j;
-
-	for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
-
-		switch (info->flash_id & FLASH_VENDMASK) {
-
-			case (INTEL_MANUFACT & FLASH_VENDMASK):
-				printf("Intel: ");
-				break;
-			default:
-				printf("Unknown Vendor ");
-				break;
-		}
-
-		switch (info->flash_id & FLASH_TYPEMASK) {
-
-			case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
-				printf("28F128J3 (128Mbit)\n");
-				break;
-			default:
-				printf("Unknown Chip Type\n");
-				return;
-		}
-
-		printf("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-		printf("  Sector Start Addresses:");
-		for (i = 0; i < info->sector_count; i++) {
-			if ((i % 5) == 0) printf ("\n   ");
-
-			printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
-		}
-		printf ("\n");
-		info++;
-	}
-}
-
-
-/**
- * flash_erase: - erase flash sectors
- *
- */
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	int rc = ERR_OK;
-	ulong start;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return ERR_UNKNOWN_FLASH_TYPE;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		return ERR_INVAL;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
-		return ERR_UNKNOWN_FLASH_VENDOR;
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) prot++;
-	}
-
-	if (prot) return ERR_PROTECTED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
-
-		printf("Erasing sector %2d ... ", sect);
-
-		PRINTK("\n");
-
-		/* arm simple, non interrupt dependent timer */
-		start = get_timer(0);
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			u16 * volatile addr = (u16 * volatile)(info->start[sect]);
-
-			PRINTK("unlocking sector\n");
-			*addr = 0x0060;
-			*addr = 0x00d0;
-			*addr = 0x00ff;
-
-			PRINTK("erasing sector\n");
-			*addr = 0x0020;
-			PRINTK("confirming erase\n");
-			*addr = 0x00D0;
-
-			while ((*addr & 0x0080) != 0x0080) {
-				PRINTK(".");
-				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					*addr = 0x00B0; /* suspend erase*/
-					*addr = 0x00FF; /* read mode    */
-					rc = ERR_TIMOUT;
-					goto outahere;
-				}
-			}
-
-			PRINTK("clearing status register\n");
-			*addr = 0x0050;
-			PRINTK("resetting to read mode");
-			*addr = 0x00FF;
-		}
-
-		printf("ok.\n");
-	}
-
-	if (ctrlc()) printf("User Interrupt!\n");
-
-	outahere:
-
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked(10000);
-
-	if (flag) enable_interrupts();
-
-	return rc;
-}
-
-
-/**
- * write_word: - copy memory to flash
- *
- * @param info:
- * @param dest:
- * @param data:
- * @return:
- */
-
-static int write_word (flash_info_t *info, ulong dest, ushort data)
-{
-	volatile u16 *addr = (u16 *)dest, val;
-	int rc = ERR_OK;
-	int flag;
-	ulong start;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) return ERR_NOT_ERASED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	flag = disable_interrupts();
-
-	/* clear status register command */
-	*addr = 0x50;
-
-	/* program set-up command */
-	*addr = 0x40;
-
-	/* latch address/data */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait while polling the status register */
-	while(((val = *addr) & 0x80) != 0x80) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = ERR_TIMOUT;
-			*addr = 0xB0; /* suspend program command */
-			goto outahere;
-		}
-	}
-
-	if(val & 0x1A) {	/* check for error */
-		printf("\nFlash write error %02x at address %08lx\n",
-			(int)val, (unsigned long)dest);
-		if(val & (1<<3)) {
-			printf("Voltage range error.\n");
-			rc = ERR_PROG_ERROR;
-			goto outahere;
-		}
-		if(val & (1<<1)) {
-			printf("Device protect error.\n");
-			rc = ERR_PROTECTED;
-			goto outahere;
-		}
-		if(val & (1<<4)) {
-			printf("Programming error.\n");
-			rc = ERR_PROG_ERROR;
-			goto outahere;
-		}
-		rc = ERR_PROG_ERROR;
-		goto outahere;
-	}
-
-	outahere:
-
-	*addr = 0xFF; /* read array command */
-	if (flag) enable_interrupts();
-
-	return rc;
-}
-
-
-/**
- * write_buf: - Copy memory to flash.
- *
- * @param info:
- * @param src:	source of copy transaction
- * @param addr:	where to copy to
- * @param cnt:	number of bytes to copy
- *
- * @return	error code
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	ushort data;
-	int l;
-	int i, rc;
-
-	wp = (addr & ~1);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
-		}
-		for (; i<2 && cnt>0; ++i) {
-			data = (data >> 8) | (*src++ << 8);
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<2; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *)cp << 8);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 2;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 2) {
-		/* data = *((vushort*)src); */
-		data = *((ushort*)src);
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		src += 2;
-		wp  += 2;
-		cnt -= 2;
-	}
-
-	if (cnt == 0) return ERR_OK;
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 8);
-		--cnt;
-	}
-	for (; i<2; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *)cp << 8);
-	}
-
-	return write_word(info, wp, data);
-}
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
deleted file mode 100644
index 22de7e3..0000000
--- a/board/innokom/innokom.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * (C) Copyright 2002
- * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
- * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
- * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/mach-types.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-/**
- * i2c_init_board - reset i2c bus. When the board is powercycled during a
- * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
- * The Innokom board has GPIO70 connected to SCLK which can be toggled
- * until all chips think that their current cycles are finished.
- */
-int i2c_init_board(void)
-{
-	int i;
-
-	/* set gpio pin low _before_ we change direction to output          */
-	writel(GPIO_bit(70), GPCR(70));
-
-	/* now toggle between output=low and high-impedance                 */
-	for (i = 0; i < 20; i++) {
-		writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70));  /* output */
-		udelay(10);
-		writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input  */
-		udelay(10);
-	}
-
-	return 0;
-}
-
-
-/**
- * misc_init_r: - misc initialisation routines
- */
-
-int misc_init_r(void)
-{
-	char *str;
-
-	/* determine if the software update key is pressed during startup   */
-	if (readl(GPLR0) & 0x00000800) {
-		printf("using bootcmd_normal (sw-update button not pressed)\n");
-		str = getenv("bootcmd_normal");
-	} else {
-		printf("using bootcmd_update (sw-update button pressed)\n");
-		str = getenv("bootcmd_update");
-	}
-
-	setenv("bootcmd",str);
-
-	return 0;
-}
-
-
-/**
- * board_init: - setup some data structures
- *
- * @return: 0 in case of success
- */
-
-int board_init (void)
-{
-	/* We have RAM, disable cache */
-	dcache_disable();
-	icache_disable();
-
-	gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
-	gd->bd->bi_boot_params = 0xa0000100;
-	gd->bd->bi_baudrate = CONFIG_BAUDRATE;
-
-	return 0;
-}
-
-extern void pxa_dram_init(void);
-int dram_init(void)
-{
-	pxa_dram_init();
-	gd->ram_size = PHYS_SDRAM_1_SIZE;
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-/**
- * innokom_set_led: - switch LEDs on or off
- *
- * @param led:   LED to switch (0,1,2)
- * @param state: switch on (1) or off (0)
- */
-
-void innokom_set_led(int led, int state)
-{
-	switch(led) {
-/*
-		case 0: if (state==1) {
-				GPCR0 |= CSB226_USER_LED0;
-			} else if (state==0) {
-				GPSR0 |= CSB226_USER_LED0;
-			}
-			break;
-
-		case 1: if (state==1) {
-				GPCR0 |= CSB226_USER_LED1;
-			} else if (state==0) {
-				GPSR0 |= CSB226_USER_LED1;
-			}
-			break;
-
-		case 2: if (state==1) {
-				GPCR0 |= CSB226_USER_LED2;
-			} else if (state==0) {
-				GPSR0 |= CSB226_USER_LED2;
-			}
-			break;
-*/
-	}
-
-	return;
-}
-
-
-/**
- * show_boot_progress: - indicate state of the boot process
- *
- * @param status: Status number - see README for details.
- *
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
- */
-
-void show_boot_progress (int status)
-{
-	switch(status) {
-/*
-		case  1: csb226_set_led(0,1); break;
-		case  5: csb226_set_led(1,1); break;
-		case 15: csb226_set_led(2,1); break;
-*/
-	}
-
-	return;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index e63625b..9f259c2 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -72,9 +72,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	/* arch number of VCMA9-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
-
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x30000100;
 
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 871b94a..b26e33a 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -248,9 +248,6 @@ int board_init(void)
 		1 << ATMEL_ID_PIOC,
 		&pmc->pcer);
 
-	/* arch number of PM9261-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_PM9261;
-
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index cfc9847..b0f7ea6 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -349,9 +349,6 @@ int board_init(void)
 		(1 << ATMEL_ID_PIOB),
 		&pmc->pcer);
 
-	/* arch number of AT91SAM9263EK-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
-
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index f3374a4..961d193 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -139,8 +139,6 @@ int board_init(void)
 		(1 << ATMEL_ID_PIOC) |
 		(1 << ATMEL_ID_PIODE), &pmc->pcer);
 
-	/* arch number of AT91SAM9M10G45EK-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
index a89ee1a..c56b195 100644
--- a/board/syteco/zmx25/zmx25.c
+++ b/board/syteco/zmx25/zmx25.c
@@ -128,7 +128,6 @@ int board_late_init(void)
 
 #ifdef CONFIG_FEC_MXC
 	struct iomuxc_mux_ctl *muxctl;
-	struct iomuxc_pad_ctl *padctl;
 	u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
 	u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
 
@@ -144,7 +143,6 @@ int board_late_init(void)
 	 * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
 	 */
 	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
 
 	writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
 	writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
diff --git a/board/innokom/Makefile b/board/ti/omap5_evm/Makefile
index 8b58b7f..fa81d64 100644
--- a/board/innokom/Makefile
+++ b/board/ti/omap5_evm/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2006
+# (C) Copyright 2000, 2001, 2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -12,7 +12,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= innokom.o flash.o
+COBJS	:= evm.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
@@ -33,6 +33,12 @@ OBJS	:= $(addprefix $(obj),$(COBJS))
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c
new file mode 100644
index 0000000..ea0cb13
--- /dev/null
+++ b/board/ti/omap5_evm/evm.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl6030.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "mux_data.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP5430 EVM\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure EVM board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_TWL6030_POWER
+	twl6030_init_battery_charging();
+#endif
+	return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
+void set_muxconf_regs_non_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	omap_mmc_init(1);
+	return 0;
+}
+#endif
diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h
new file mode 100644
index 0000000..18f4729
--- /dev/null
+++ b/board/ti/omap5_evm/mux_data.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ *	Balaji Krishnamoorthy	<balajitk@ti.com>
+ *	Aneesh V		<aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EVM5430_MUX_DATA_H
+#define _EVM5430_MUX_DATA_H
+
+#include <asm/arch/mux_omap5.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
+	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
+	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
+	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
+	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
+	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
+	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
+	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
+	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
+	{GPMC_A16, (M3)},						/* gpio_40 */
+	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
+	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
+	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
+	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
+	{GPMC_A21, (M3)},						/* gpio_45 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
+	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
+	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
+	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
+	{GPMC_NCS0, (M3)},						/* gpio_50 */
+	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
+	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
+	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
+	{GPMC_NWP, (M3)},						/* gpio_54 */
+	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
+	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
+	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
+	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
+	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
+	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
+	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
+	{C2C_DATA14, (M1)},						/* dsi2_te0 */
+	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
+	{HDMI_HPD, (M0)},						/* hdmi_hpd */
+	{HDMI_CEC, (M0)},						/* hdmi_cec */
+	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
+	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
+	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
+	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
+	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
+	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
+	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
+	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
+	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
+	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
+	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
+	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
+	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
+	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
+	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
+	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
+	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
+	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
+	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
+	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
+	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
+	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
+	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
+	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
+	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
+	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
+	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
+	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
+	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
+	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
+	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
+	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
+	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
+	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
+	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
+	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
+	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
+	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
+	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
+	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
+	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
+	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
+	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
+	{UART2_RTS, (M0)},						/* uart2_rts */
+	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
+	{UART2_TX, (M0)},						/* uart2_tx */
+	{HDQ_SIO, (M3)},						/* gpio_127 */
+	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
+	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
+	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
+	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
+	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
+	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
+	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
+	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
+	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
+	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
+	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
+	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
+	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
+	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
+	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
+	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
+	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
+	{UART4_RX, (IEN | M0)},						/* uart4_rx */
+	{UART4_TX, (M0)},						/* uart4_tx */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
+	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
+	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
+	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
+	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
+	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
+	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
+	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
+	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
+	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
+	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
+	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
+	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
+	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
+	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
+	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
+	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
+	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
+	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
+	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
+	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
+	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
+	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
+	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
+	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
+	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
+	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
+	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
+	{SYS_BOOT1, (M3)},						/* gpio_185 */
+	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
+	{SYS_BOOT4, (M3)},						/* gpio_188 */
+	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
+	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
+	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
+	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
+	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
+	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
+	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
+	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
+	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
+	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
+	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
+	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
+	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
+	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
+	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
+	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
+	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
+	{DPM_EMU16, (M3)},						/* gpio_27 */
+	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
+	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
+	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
+	{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+	{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+	{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+	{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)}				/* i2c4_sda */
+};
+
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
+};
+
+#endif /* _EVM4430_MUX_DATA_H */
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
index ec493f5..b299e2f 100644
--- a/board/ti/panda/Makefile
+++ b/board/ti/panda/Makefile
@@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-ifndef CONFIG_SPL_BUILD
 COBJS	:= panda.o
-endif
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 97320cb..b4271fb 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -65,6 +65,23 @@ int misc_init_r(void)
 	return 0;
 }
 
+void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	if (omap_revision() >= OMAP4460_ES1_0)
+		do_set_mux(CONTROL_PADCONF_WKUP,
+				 wkup_padconf_array_essential_4460,
+				 sizeof(wkup_padconf_array_essential_4460) /
+				 sizeof(struct pad_conf_entry));
+}
+
 void set_muxconf_regs_non_essential(void)
 {
 	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
@@ -93,10 +110,18 @@ void set_muxconf_regs_non_essential(void)
 				sizeof(struct pad_conf_entry));
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0);
 	return 0;
 }
 #endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index 83d0c3f..c05170e 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -28,6 +28,58 @@
 
 #include <asm/arch/mux_omap4.h>
 
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)},	 /* gpio_wk7, TPS */
+
+};
+
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
@@ -219,7 +271,7 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
 	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
 	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, M7},					/* safe mode */
+	{PAD1_FREF_CLK3_REQ, M7},		/* safe mode */
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
 	{PAD0_FREF_CLK4_OUT, (PTU | M3)},	/* led status_2 */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
index 806fdf4..72ad3eb 100644
--- a/board/ti/sdp4430/Makefile
+++ b/board/ti/sdp4430/Makefile
@@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+COBJS	:= sdp.o
+
 ifndef CONFIG_SPL_BUILD
-COBJS	:= sdp.o cmd_bat.o
+COBJS	+= cmd_bat.o
 endif
 
 SRCS	:= $(COBJS:.o=.c)
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index a5ea682..e1b853c 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -70,6 +70,23 @@ int misc_init_r(void)
 	return 0;
 }
 
+void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	if (omap_revision() >= OMAP4460_ES1_0)
+		do_set_mux(CONTROL_PADCONF_WKUP,
+				 wkup_padconf_array_essential_4460,
+				 sizeof(wkup_padconf_array_essential_4460) /
+				 sizeof(struct pad_conf_entry));
+}
+
 void set_muxconf_regs_non_essential(void)
 {
 	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
@@ -81,7 +98,7 @@ void set_muxconf_regs_non_essential(void)
 		   sizeof(struct pad_conf_entry));
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0);
@@ -89,3 +106,11 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 #endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
index 06efaea..1c6e0ee 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -28,6 +28,49 @@
 
 #include <asm/arch/mux_omap4.h>
 
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
+{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
+{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)},	 /* gpio_wk7, TPS */
+
+};
+
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
 	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
@@ -200,6 +243,15 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
 	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
 	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
+	{I2C1_SCL, (PTU | IEN | M0)},					/* i2c1_scl */
+	{I2C1_SDA, (PTU | IEN | M0)},					/* i2c1_sda */
+	{I2C2_SCL, (PTU | IEN | M0)},					/* i2c2_scl */
+	{I2C2_SDA, (PTU | IEN | M0)},					/* i2c2_sda */
+	{I2C3_SCL, (PTU | IEN | M0)},					/* i2c3_scl */
+	{I2C3_SDA, (PTU | IEN | M0)},					/* i2c3_sda */
+	{I2C4_SCL, (PTU | IEN | M0)},					/* i2c4_scl */
+	{I2C4_SDA, (PTU | IEN | M0)}					/* i2c4_sda */
+
 };
 
 const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
@@ -214,7 +266,6 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
 	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 - Debug led-1 */
 	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 - Debug led-2 */
 	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 - Debug led-3 */
 	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
 	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 43bbdff..cf8e7b6 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -21,6 +21,7 @@
 
 #include <common.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
 #include <netdev.h>
 #include <serial.h>
 #include <asm/io.h>
@@ -72,6 +73,14 @@ void dram_init_banksize(void)
 #endif
 }
 
+#ifdef	CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
+
 #ifdef	CONFIG_CMD_USB
 int usb_board_init(void)
 {