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| author | Liu Gang <Gang.Liu@freescale.com> | 2013-05-07 16:30:50 +0800 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-06-20 17:08:49 -0500 |
| commit | 69fdf900105d9f730b526c760c082d1f6641a489 (patch) | |
| tree | 9d6c51856acdfe121c61b5de82028c797e346b55 /board | |
| parent | 3e531b0ba96590ab3e86ee3b5c9fa8a2e91b6849 (diff) | |
| download | u-boot-imx-69fdf900105d9f730b526c760c082d1f6641a489.zip u-boot-imx-69fdf900105d9f730b526c760c082d1f6641a489.tar.gz u-boot-imx-69fdf900105d9f730b526c760c082d1f6641a489.tar.bz2 | |
powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/t4qds/tlb.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 92c01cf..a138d5a 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -55,6 +55,15 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -130,6 +139,16 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif }; |