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| author | Stephen George <stephen.george@freescale.com> | 2013-03-25 07:40:12 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-24 16:54:12 -0500 |
| commit | 49e946cb6ae0448492147ffcb9dcd7d0af1eab4d (patch) | |
| tree | 07118135410c7b399c8ac780b6fa803ceebdfaea /board | |
| parent | 94025b1cd8d9959ebf987a7f6382d513c606ecf1 (diff) | |
| download | u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.zip u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.tar.gz u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.tar.bz2 | |
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/b4860qds/law.c | 3 | ||||
| -rw-r--r-- | board/freescale/b4860qds/tlb.c | 2 | ||||
| -rw-r--r-- | board/freescale/t4qds/law.c | 3 | ||||
| -rw-r--r-- | board/freescale/t4qds/tlb.c | 2 |
4 files changed, 6 insertions, 4 deletions
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c index 4142e01..abaad7a 100644 --- a/board/freescale/b4860qds/law.c +++ b/board/freescale/b4860qds/law.c @@ -34,7 +34,8 @@ struct law_entry law_table[] = { #endif SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 6d634bf..29cc41b 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -106,7 +106,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4M, 1), + 0, 10, BOOKE_PAGESZ_32M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c index 6f2c5c8..f3848f3 100644 --- a/board/freescale/t4qds/law.c +++ b/board/freescale/t4qds/law.c @@ -37,7 +37,8 @@ struct law_entry law_table[] = { #endif SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 80eb511..92c01cf 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -115,7 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), + 0, 13, BOOKE_PAGESZ_32M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* |