diff options
| author | Adrian Alonso <adrian.alonso@nxp.com> | 2016-01-20 15:16:08 -0600 |
|---|---|---|
| committer | guoyin.chen <guoyin.chen@freescale.com> | 2016-03-04 15:35:57 +0800 |
| commit | 21c6f85d0023a5c7edf17b31d4334beb966d8059 (patch) | |
| tree | c7eb9ec8e611096b688bfaf721079394995764ad /board | |
| parent | 742ab69302700dc9137329b4773de1aa0f5df89f (diff) | |
MLK-12442: imx: mx6qarm2: lpddr2 set dram 2 channel fixed mode
Setup MMDC in two channel fixed mode
Initialize dram banks for two channel fixed mode
DRAM bank = 0x00000000
-> start = 0x10000000
-> size = 0x20000000
DRAM bank = 0x00000001
-> start = 0x80000000
-> size = 0x20000000
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mx6qarm2/mt128x64mx32.cfg | 4 | ||||
| -rw-r--r-- | board/freescale/mx6qarm2/mx6qarm2.c | 9 |
2 files changed, 11 insertions, 2 deletions
diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg index adc8c4b..35a686f 100644 --- a/board/freescale/mx6qarm2/mt128x64mx32.cfg +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -209,7 +209,7 @@ DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC -DATA 4 0x021b0040 0x00000053 // Chan0 CS0_END 2 channel with 4K-interleave mode +DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END 2 channel with 2 Channel fixed mode // DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL @@ -224,7 +224,7 @@ DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC -DATA 4 0x021b4040 0x00000013 // Chan1 CS0_END +DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END // DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 188096b..72f59ef 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -47,6 +47,15 @@ int dram_init(void) return 0; } +#if defined(CONFIG_MX6DQ_POP_LPDDR2) +void dram_init_banksize(void) { + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; +} +#endif + iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |