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| author | Stefan Roese <sr@denx.de> | 2007-07-24 07:20:09 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-07-24 07:44:12 +0200 |
| commit | aedf5bde179ecfbd0a96130d18996a96518b785f (patch) | |
| tree | 6bb4a0725bf63a4a71bd006e9713be0bc073f8c9 /board | |
| parent | a71d96eac8130b53a91f93cd10c70fca0db18d52 (diff) | |
| download | u-boot-imx-aedf5bde179ecfbd0a96130d18996a96518b785f.zip u-boot-imx-aedf5bde179ecfbd0a96130d18996a96518b785f.tar.gz u-boot-imx-aedf5bde179ecfbd0a96130d18996a96518b785f.tar.bz2 | |
ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...)
As suggested by Hakan Eryigit, here an updated setup for the lwmon5
interrupt controller.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/lwmon5/lwmon5.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index b7dbba3..5c4cf9d 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -45,16 +45,16 @@ int board_early_init_f(void) mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ mtdcr(uic0er, 0x00000000); /* disable all */ mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ - mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */ - mtdcr(uic0tr, 0x00000810); /* per ref-board manual */ + mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ + mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(uic0sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1er, 0x00000000); /* disable all */ mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */ - mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */ + mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ + mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ mtdcr(uic1sr, 0xffffffff); /* clear all */ @@ -62,9 +62,9 @@ int board_early_init_f(void) mtdcr(uic2er, 0x00000000); /* disable all */ mtdcr(uic2cr, 0x00000000); /* all non-critical */ mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ - mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */ + mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ /* Trace Pins are disabled. SDR0_PFC0 Register */ mtsdr(SDR0_PFC0, 0x0); |