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| author | Bin Meng <bmeng.cn@gmail.com> | 2014-12-17 15:50:45 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2014-12-18 17:26:07 -0700 |
| commit | 0ff65eb99c3ed4d452b9c74dae8c4f736d92303f (patch) | |
| tree | da2213025260185c6aa4c14ad2d3b3de995fd25b /board | |
| parent | adfe3b247a7a281931f0fd865e9d00600e9dd384 (diff) | |
| download | u-boot-imx-0ff65eb99c3ed4d452b9c74dae8c4f736d92303f.zip u-boot-imx-0ff65eb99c3ed4d452b9c74dae8c4f736d92303f.tar.gz u-boot-imx-0ff65eb99c3ed4d452b9c74dae8c4f736d92303f.tar.bz2 | |
x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/intel/crownbay/crownbay.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index 54670d3..2a254ef 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/ibmpc.h> #include <asm/pnp_def.h> +#include <netdev.h> #include <smsc_lpc47m.h> #define SERIAL_DEV PNP_DEV(0x2e, 4) @@ -24,3 +25,8 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} |