diff options
| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2012-08-08 03:55:32 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2012-09-23 19:57:13 +0200 |
| commit | 5527024fdb10798d2975197f287457b29e2d4084 (patch) | |
| tree | 2255a6b8aab740717826f9b28462fdb8baa82529 /board | |
| parent | 362635bd50e386770ebaa2d5d090eb8cbf96430b (diff) | |
| download | u-boot-imx-5527024fdb10798d2975197f287457b29e2d4084.zip u-boot-imx-5527024fdb10798d2975197f287457b29e2d4084.tar.gz u-boot-imx-5527024fdb10798d2975197f287457b29e2d4084.tar.bz2 | |
KARO TX25: Fix NAND Flash R/W cycle times
The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W
cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using
the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle)
resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses.
This patch fixes this issue by setting the NFC clock to the highest frequency
complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Gachet <Daniel.Gachet@hefr.ch>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/karo/tx25/lowlevel_init.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S index 823df10..eb3f187 100644 --- a/board/karo/tx25/lowlevel_init.S +++ b/board/karo/tx25/lowlevel_init.S @@ -67,6 +67,14 @@ write32 0x53f80008, 0x20034000 /* + * PCDR2: NFC = 33.25 MHz + * This is required for the NAND Flash of this board, which is a Samsung + * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with + * the NFC driver in symmetric (i.e. one-cycle) mode. + */ + write32 0x53f80020, 0x01010103 + + /* * enable all implemented clocks in all three * clock control registers */ |