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| author | Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> | 2014-07-09 23:44:44 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-07-25 16:26:10 -0400 |
| commit | 3d315386255f6d944c0ccb4c7c8819ce604429ab (patch) | |
| tree | 58799564ac6044eecbb23a92350bcae688065841 /board | |
| parent | 7b26c1f608d3ef18b11ff0a07476155af4a6ab95 (diff) | |
| download | u-boot-imx-3d315386255f6d944c0ccb4c7c8819ce604429ab.zip u-boot-imx-3d315386255f6d944c0ccb4c7c8819ce604429ab.tar.gz u-boot-imx-3d315386255f6d944c0ccb4c7c8819ce604429ab.tar.bz2 | |
k2hk: use common KS2_ prefix for all hardware definitions
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.
Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/ti/k2hk_evm/ddr3.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index b604266..31e9c31 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -299,20 +299,20 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_64A_pg2); } else { /* PG 1.1 */ - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_64A); } - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); } else { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); } @@ -323,18 +323,18 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_64A_pg2); } else { /* PG 1.1 */ - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_64A); } - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); } else { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32); } } else { @@ -344,6 +344,6 @@ void ddr3_init(void) } init_pll(&ddr3b_333); - ddr3_init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); - ddr3_init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); + ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); + ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); } |