ENGR00320057 iMX6SX:SABRESD/19x19ARM2: Update DDR3 scripts

Update latest DDR3 scirpts for imx6sx SabreSD and 19x19 DDR3 ARM2 board
as provided by board team.
(http://sw-git.freescale.net/cgi-bin/gitweb.cgi?p=ddr-scripts-rel.git)

Signed-off-by: Ye.Li <B37916@freescale.com>

4 files changed, 136 insertions, 70 deletions

diff --git a/board/freescale/mx6sx_19x19_arm2/imximage.cfg b/board/freescale/mx6sx_19x19_arm2/imximage.cfg
index 613a916..475127c 100644
--- a/board/freescale/mx6sx_19x19_arm2/imximage.cfg
+++ b/board/freescale/mx6sx_19x19_arm2/imximage.cfg
@@ -50,6 +50,7 @@ CSF 0x2000
  *	value	  value to be stored in the register
  */
 
+/* Enable all clocks */
 DATA 4 0x020c4068 0xffffffff
 DATA 4 0x020c406c 0xffffffff
 DATA 4 0x020c4070 0xffffffff
@@ -59,13 +60,20 @@ DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 DATA 4 0x020c4084 0xffffffff
 
+/* IOMUX */
+/* DDR IO TYPE */
 DATA 4 0x020e0618 0x000c0000
 DATA 4 0x020e05fc 0x00000000
+
+/* CLOCK */
 DATA 4 0x020e032c 0x00000030
 
+/* ADDRESS */
 DATA 4 0x020e0300 0x00000030
 DATA 4 0x020e02fc 0x00000030
 DATA 4 0x020e05f4 0x00000030
+
+/* CONTROL */
 DATA 4 0x020e0340 0x00000030
 
 DATA 4 0x020e0320 0x00000000
@@ -73,11 +81,14 @@ DATA 4 0x020e0310 0x00000030
 DATA 4 0x020e0314 0x00000030
 DATA 4 0x020e0614 0x00000030
 
+/* DATA STROBE */
 DATA 4 0x020e05f8 0x00020000
 DATA 4 0x020e0330 0x00000030
 DATA 4 0x020e0334 0x00000030
 DATA 4 0x020e0338 0x00000030
 DATA 4 0x020e033c 0x00000030
+
+/* DATA */
 DATA 4 0x020e0608 0x00020000
 DATA 4 0x020e060c 0x00000030
 DATA 4 0x020e0610 0x00000030
@@ -87,18 +98,35 @@ DATA 4 0x020e02ec 0x00000030
 DATA 4 0x020e02f0 0x00000030
 DATA 4 0x020e02f4 0x00000030
 DATA 4 0x020e02f8 0x00000030
+
+/* Calibrations */
+/* ZQ */
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x00270025
-DATA 4 0x021b0810 0x001B001E
-DATA 4 0x021b083c 0x4144013C
-DATA 4 0x021b0840 0x01300128
-DATA 4 0x021b0848 0x4044464A
-DATA 4 0x021b0850 0x3A383C34
+/* write leveling */
+DATA 4 0x021b080c 0x002C003D
+DATA 4 0x021b0810 0x00110046
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4160016C
+DATA 4 0x021b0840 0x013C016C
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x46424446
+DATA 4 0x021b0850 0x3A3C3C3A
+
+DATA 4 0x021b08c0 0x2492244A
+
+/* read data bit delay */
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
 DATA 4 0x021b0824 0x33333333
 DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurment */
 DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init */
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
 DATA 4 0x021b0004 0x0002002d
 DATA 4 0x021b0008 0x00333030
 DATA 4 0x021b000c 0x676b52f3
@@ -108,15 +136,26 @@ DATA 4 0x021b0018 0x00011740
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b002c 0x000026d2
 DATA 4 0x021b0030 0x006b1023
-DATA 4 0x021b0040 0x0000005f
-DATA 4 0x021b0000 0x84190000
+DATA 4 0x021b0040 0x0000007f
+DATA 4 0x021b0000 0x85190000
+
+/* Initialize CS0: MT41K256M16HA-125 */
+/* MR2 */
 DATA 4 0x021b001c 0x04008032
+/* MR3 */
 DATA 4 0x021b001c 0x00008033
+/* MR1 */
 DATA 4 0x021b001c 0x00068031
+/* MR0 */
 DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
 DATA 4 0x021b001c 0x04008040
+
+/* final DDR setup, before operation start */
 DATA 4 0x021b0020 0x00000800
-DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b0404 0x00011006
 DATA 4 0x021b001c 0x00000000
 
 #endif
diff --git a/board/freescale/mx6sx_19x19_arm2/plugin.S b/board/freescale/mx6sx_19x19_arm2/plugin.S
index d384aeb..191fe5b 100644
--- a/board/freescale/mx6sx_19x19_arm2/plugin.S
+++ b/board/freescale/mx6sx_19x19_arm2/plugin.S
@@ -51,18 +51,20 @@
 	ldr r0, =MMDC_P0_BASE_ADDR
 	ldr r2, =0xa1390003
 	str r2, [r0, #0x800]
-	ldr r2, =0x00270025
+	ldr r2, =0x002C003D
 	str r2, [r0, #0x80c]
-	ldr r2, =0x001B001E
+	ldr r2, =0x00110046
 	str r2, [r0, #0x810]
-	ldr r2, =0x4144013C
+	ldr r2, =0x4160016C
 	str r2, [r0, #0x83c]
-	ldr r2, =0x01300128
+	ldr r2, =0x013C016C
 	str r2, [r0, #0x840]
-	ldr r2, =0x4044464A
+	ldr r2, =0x46424446
 	str r2, [r0, #0x848]
-	ldr r2, =0x3A383C34
+	ldr r2, =0x3A3C3C3A
 	str r2, [r0, #0x850]
+	ldr r2, =0x2492244A
+	str r2, [r0, #0x8c0]
 
 	ldr r2, =0x33333333
 	str r2, [r0, #0x81c]
@@ -90,9 +92,9 @@
 	str r2, [r0, #0x02c]
 	ldr r2, =0x006b1023
 	str r2, [r0, #0x030]
-	ldr r2, =0x0000005f
+	ldr r2, =0x0000007f
 	str r2, [r0, #0x040]
-	ldr r2, =0x84190000
+	ldr r2, =0x85190000
 	str r2, [r0, #0x000]
 	ldr r2, =0x04008032
 	str r2, [r0, #0x01c]
@@ -106,8 +108,12 @@
 	str r2, [r0, #0x01c]
 	ldr r2, =0x00000800
 	str r2, [r0, #0x020]
-	ldr r2, =0x00011117
+	ldr r2, =0x00022227
 	str r2, [r0, #0x818]
+	ldr r2, =0x0002556d
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
 	ldr r2, =0x00000000
 	str r2, [r0, #0x01c]
 
diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg
index df672da..5456155 100644
--- a/board/freescale/mx6sxsabresd/imximage.cfg
+++ b/board/freescale/mx6sxsabresd/imximage.cfg
@@ -48,6 +48,7 @@ CSF 0x2000
  *	value	  value to be stored in the register
  */
 
+/* Enable all clocks */
 DATA 4 0x020c4068 0xffffffff
 DATA 4 0x020c406c 0xffffffff
 DATA 4 0x020c4070 0xffffffff
@@ -57,46 +58,72 @@ DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 DATA 4 0x020c4084 0xffffffff
 
+/* IOMUX */
+/* DDR IO TYPE */
 DATA 4 0x020e0618 0x000c0000
 DATA 4 0x020e05fc 0x00000000
+
+/* CLOCK */
 DATA 4 0x020e032c 0x00000030
 
-DATA 4 0x020e0300 0x00000030
-DATA 4 0x020e02fc 0x00000030
-DATA 4 0x020e05f4 0x00000030
-DATA 4 0x020e0340 0x00000030
+/* ADDRESS */
+DATA 4 0x020e0300 0x00000020
+DATA 4 0x020e02fc 0x00000020
+DATA 4 0x020e05f4 0x00000020
+
+/* CONTROL */
+DATA 4 0x020e0340 0x00000020
 
 DATA 4 0x020e0320 0x00000000
-DATA 4 0x020e0310 0x00000030
-DATA 4 0x020e0314 0x00000030
-DATA 4 0x020e0614 0x00000030
+DATA 4 0x020e0310 0x00000020
+DATA 4 0x020e0314 0x00000020
+DATA 4 0x020e0614 0x00000020
 
+/* DATA STROBE */
 DATA 4 0x020e05f8 0x00020000
-DATA 4 0x020e0330 0x00000030
-DATA 4 0x020e0334 0x00000030
-DATA 4 0x020e0338 0x00000030
-DATA 4 0x020e033c 0x00000030
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* DATA */
 DATA 4 0x020e0608 0x00020000
-DATA 4 0x020e060c 0x00000030
-DATA 4 0x020e0610 0x00000030
-DATA 4 0x020e061c 0x00000030
-DATA 4 0x020e0620 0x00000030
-DATA 4 0x020e02ec 0x00000030
-DATA 4 0x020e02f0 0x00000030
-DATA 4 0x020e02f4 0x00000030
-DATA 4 0x020e02f8 0x00000030
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations */
+/* ZQ */
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x00270025
-DATA 4 0x021b0810 0x001B001E
-DATA 4 0x021b083c 0x4144013C
-DATA 4 0x021b0840 0x01300128
-DATA 4 0x021b0848 0x4044464A
-DATA 4 0x021b0850 0x3A383C34
+
+/* write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00220022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x41480144
+DATA 4 0x021b0840 0x01340130
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x3C3E4244
+DATA 4 0x021b0850 0x34363638
+
+/* read data bit delay */
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
 DATA 4 0x021b0824 0x33333333
 DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurment */
 DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init */
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
 DATA 4 0x021b0004 0x0002002d
 DATA 4 0x021b0008 0x00333030
 DATA 4 0x021b000c 0x676b52f3
@@ -108,18 +135,21 @@ DATA 4 0x021b002c 0x000026d2
 DATA 4 0x021b0030 0x006b1023
 DATA 4 0x021b0040 0x0000005f
 DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 */
+/* MR2 */
 DATA 4 0x021b001c 0x04008032
+/* MR3 */
 DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00068031
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
 DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
 DATA 4 0x021b001c 0x04008040
+
+/* final DDR setup, before operation start */
 DATA 4 0x021b0020 0x00000800
 DATA 4 0x021b0818 0x00011117
 DATA 4 0x021b001c 0x00000000
-
-DATA 4 0x021b083c 0x41400138
-DATA 4 0x021b0840 0x012C011C
-DATA 4 0x021b0848 0x3C3C4044
-DATA 4 0x021b0850 0x34343638
-
 #endif
diff --git a/board/freescale/mx6sxsabresd/plugin.S b/board/freescale/mx6sxsabresd/plugin.S
index 2ec603d..667095f 100644
--- a/board/freescale/mx6sxsabresd/plugin.S
+++ b/board/freescale/mx6sxsabresd/plugin.S
@@ -16,7 +16,7 @@
 	ldr r1, =0x00000030
 	str r1, [r0, #0x32c]
 
-	ldr r1, =0x00000030
+	ldr r1, =0x00000020
 	str r1, [r0, #0x300]
 	str r1, [r0, #0x2fc]
 	str r1, [r0, #0x5f4]
@@ -24,21 +24,21 @@
 
 	ldr r1, =0x00000000
 	str r1, [r0, #0x320]
-	ldr r1, =0x00000030
+	ldr r1, =0x00000020
 	str r1, [r0, #0x310]
 	str r1, [r0, #0x314]
 	str r1, [r0, #0x614]
 
 	ldr r1, =0x00020000
 	str r1, [r0, #0x5f8]
-	ldr r1, =0x00000030
+	ldr r1, =0x00000028
 	str r1, [r0, #0x330]
 	str r1, [r0, #0x334]
 	str r1, [r0, #0x338]
 	str r1, [r0, #0x33c]
 	ldr r1, =0x00020000
 	str r1, [r0, #0x608]
-	ldr r1, =0x00000030
+	ldr r1, =0x00000028
 	str r1, [r0, #0x60c]
 	str r1, [r0, #0x610]
 	str r1, [r0, #0x61c]
@@ -51,17 +51,17 @@
 	ldr r0, =MMDC_P0_BASE_ADDR
 	ldr r2, =0xa1390003
 	str r2, [r0, #0x800]
-	ldr r2, =0x00270025
+	ldr r2, =0x00290025
 	str r2, [r0, #0x80c]
-	ldr r2, =0x001B001E
+	ldr r2, =0x00220022
 	str r2, [r0, #0x810]
-	ldr r2, =0x4144013C
+	ldr r2, =0x41480144
 	str r2, [r0, #0x83c]
-	ldr r2, =0x01300128
+	ldr r2, =0x01340130
 	str r2, [r0, #0x840]
-	ldr r2, =0x4044464A
+	ldr r2, =0x3C3E4244
 	str r2, [r0, #0x848]
-	ldr r2, =0x3A383C34
+	ldr r2, =0x34363638
 	str r2, [r0, #0x850]
 
 	ldr r2, =0x33333333
@@ -98,7 +98,7 @@
 	str r2, [r0, #0x01c]
 	ldr r2, =0x00008033
 	str r2, [r0, #0x01c]
-	ldr r2, =0x00068031
+	ldr r2, =0x00048031
 	str r2, [r0, #0x01c]
 	ldr r2, =0x05208030
 	str r2, [r0, #0x01c]
@@ -110,15 +110,6 @@
 	str r2, [r0, #0x818]
 	ldr r2, =0x00000000
 	str r2, [r0, #0x01c]
-
-	ldr r2, =0x41400138
-	str r2, [r0, #0x83c]
-	ldr r2, =0x012C011C
-	str r2, [r0, #0x840]
-	ldr r2, =0x3C3C4044
-	str r2, [r0, #0x848]
-	ldr r2, =0x34343638
-	str r2, [r0, #0x850]
 .endm
 .macro imx6_clock_gating
 	ldr r0, =CCM_BASE_ADDR