Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

61 files changed, 1949 insertions, 987 deletions

diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile
index 5b95682..52d0d3c 100644
--- a/board/ads5121/Makefile
+++ b/board/ads5121/Makefile
@@ -27,7 +27,7 @@ $(shell mkdir -p $(OBJTREE)/board/freescale/common)
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS-y	:= $(BOARD).o iopin.o
+COBJS-y	:= $(BOARD).o
 COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o
 COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o
 COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 8452054..ba3d7d2 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -23,14 +23,12 @@
 
 #include <common.h>
 #include <mpc512x.h>
-#include "iopin.h"
 #include <asm/bitops.h>
 #include <command.h>
 #include <fdt_support.h>
 #ifdef CONFIG_MISC_INIT_R
 #include <i2c.h>
 #endif
-#include "iopin.h"	/* for iopin_initialize() prototype */
 
 /* Clocks in use */
 #define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
@@ -124,7 +122,7 @@ long int fixed_sdram (void)
 	u32 i;
 
 	/* Initialize IO Control */
-	im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
+	im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
 
 	/* Initialize DDR Local Window */
 	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
@@ -237,6 +235,56 @@ int misc_init_r(void)
 
 	return 0;
 }
+static  iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		IOCTL_SPDIF_TXCLK, 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* Set highest Slew on 9 PATA pins */
+	{
+		IOCTL_PATA_CE1, 9, 1,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		IOCTL_PSC0_0, 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SPDIF_TXCLK */
+	{
+		IOCTL_LPC_CS1, 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+	{
+		IOCTL_I2C1_SCL, 2, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU CLK */
+	{
+		IOCTL_PSC6_0, 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		IOCTL_PSC6_1, 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		IOCTL_PSC6_4, 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
 
 int checkboard (void)
 {
@@ -246,7 +294,9 @@ int checkboard (void)
 	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 		brd_rev, cpld_rev);
 	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-	iopin_initialize();
+
+
+	iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
 
 	return 0;
 }
diff --git a/board/ads5121/iopin.c b/board/ads5121/iopin.c
deleted file mode 100644
index a6792a0..0000000
--- a/board/ads5121/iopin.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2008
- * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
- * mpc512x I/O pin/pad initialization for the ADS5121 board
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include "iopin.h"
-
-/* IO pin fields */
-#define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
-#define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
-#define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
-#define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
-#define IO_PIN_ST(v)	((v) << 2)	/* schmitt trigger */
-#define IO_PIN_DS(v)	((v))		/* slew rate */
-
-static struct iopin_t {
-	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
-	int nr_pins;		/* number of pins to set this way */
-	int bit_or;		/* or in the value instead of overwrite */
-	u_long val;		/* value to write or or */
-} ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		IOCTL_SPDIF_TXCLK, 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* Set highest Slew on 9 PATA pins */
-	{
-		IOCTL_PATA_CE1, 9, 1,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		IOCTL_PSC0_0, 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SPDIF_TXCLK */
-	{
-		IOCTL_LPC_CS1, 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
-	{
-		IOCTL_I2C1_SCL, 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU CLK */
-	{
-		IOCTL_PSC6_0, 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		IOCTL_PSC6_1, 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		IOCTL_PSC6_4, 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-void iopin_initialize(void)
-{
-	short i, j, n, p;
-	u_long *reg;
-	immap_t *im = (immap_t *)CFG_IMMR;
-
-	reg = (u_long *)&(im->io_ctrl.regs[0]);
-
-	if (sizeof(ioregs_init) == 0)
-		return;
-
-	n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
-
-	for (i = 0; i < n; i++) {
-		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
-			p < ioregs_init[i].nr_pins; p++, j++) {
-			if (ioregs_init[i].bit_or)
-				reg[j] |= ioregs_init[i].val;
-			else
-				reg[j] = ioregs_init[i].val;
-		}
-	}
-	return;
-}
diff --git a/board/ads5121/iopin.h b/board/ads5121/iopin.h
deleted file mode 100644
index 7ef8472..0000000
--- a/board/ads5121/iopin.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * (C) Copyright 2008
- * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
- * mpc512x I/O pin/pad initialization for the ADS5121 board
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#define IOCTL_MEM		0x000
-#define IOCTL_GP		0x004
-#define IOCTL_LPC_CLK		0x008
-#define IOCTL_LPC_OE		0x00C
-#define IOCTL_LPC_RWB		0x010
-#define IOCTL_LPC_ACK		0x014
-#define IOCTL_LPC_CS0		0x018
-#define IOCTL_NFC_CE0		0x01C
-#define IOCTL_LPC_CS1		0x020
-#define IOCTL_LPC_CS2		0x024
-#define IOCTL_LPC_AX03		0x028
-#define IOCTL_EMB_AX02		0x02C
-#define IOCTL_EMB_AX01		0x030
-#define IOCTL_EMB_AX00		0x034
-#define IOCTL_EMB_AD31		0x038
-#define IOCTL_EMB_AD30		0x03C
-#define IOCTL_EMB_AD29		0x040
-#define IOCTL_EMB_AD28		0x044
-#define IOCTL_EMB_AD27		0x048
-#define IOCTL_EMB_AD26		0x04C
-#define IOCTL_EMB_AD25		0x050
-#define IOCTL_EMB_AD24		0x054
-#define IOCTL_EMB_AD23		0x058
-#define IOCTL_EMB_AD22		0x05C
-#define IOCTL_EMB_AD21		0x060
-#define IOCTL_EMB_AD20		0x064
-#define IOCTL_EMB_AD19		0x068
-#define IOCTL_EMB_AD18		0x06C
-#define IOCTL_EMB_AD17		0x070
-#define IOCTL_EMB_AD16		0x074
-#define IOCTL_EMB_AD15		0x078
-#define IOCTL_EMB_AD14		0x07C
-#define IOCTL_EMB_AD13		0x080
-#define IOCTL_EMB_AD12		0x084
-#define IOCTL_EMB_AD11		0x088
-#define IOCTL_EMB_AD10		0x08C
-#define IOCTL_EMB_AD09		0x090
-#define IOCTL_EMB_AD08		0x094
-#define IOCTL_EMB_AD07		0x098
-#define IOCTL_EMB_AD06		0x09C
-#define IOCTL_EMB_AD05		0x0A0
-#define IOCTL_EMB_AD04		0x0A4
-#define IOCTL_EMB_AD03		0x0A8
-#define IOCTL_EMB_AD02		0x0AC
-#define IOCTL_EMB_AD01		0x0B0
-#define IOCTL_EMB_AD00		0x0B4
-#define IOCTL_PATA_CE1		0x0B8
-#define IOCTL_PATA_CE2		0x0BC
-#define IOCTL_PATA_ISOLATE	0x0C0
-#define IOCTL_PATA_IOR		0x0C4
-#define IOCTL_PATA_IOW		0x0C8
-#define IOCTL_PATA_IOCHRDY	0x0CC
-#define IOCTL_PATA_INTRQ	0x0D0
-#define IOCTL_PATA_DRQ		0x0D4
-#define IOCTL_PATA_DACK		0x0D8
-#define IOCTL_NFC_WP		0x0DC
-#define IOCTL_NFC_RB		0x0E0
-#define IOCTL_NFC_ALE		0x0E4
-#define IOCTL_NFC_CLE		0x0E8
-#define IOCTL_NFC_WE		0x0EC
-#define IOCTL_NFC_RE		0x0F0
-#define IOCTL_PCI_AD31		0x0F4
-#define IOCTL_PCI_AD30		0x0F8
-#define IOCTL_PCI_AD29		0x0FC
-#define IOCTL_PCI_AD28		0x100
-#define IOCTL_PCI_AD27		0x104
-#define IOCTL_PCI_AD26		0x108
-#define IOCTL_PCI_AD25		0x10C
-#define IOCTL_PCI_AD24		0x110
-#define IOCTL_PCI_AD23		0x114
-#define IOCTL_PCI_AD22		0x118
-#define IOCTL_PCI_AD21		0x11C
-#define IOCTL_PCI_AD20		0x120
-#define IOCTL_PCI_AD19		0x124
-#define IOCTL_PCI_AD18		0x128
-#define IOCTL_PCI_AD17		0x12C
-#define IOCTL_PCI_AD16		0x130
-#define IOCTL_PCI_AD15		0x134
-#define IOCTL_PCI_AD14		0x138
-#define IOCTL_PCI_AD13		0x13C
-#define IOCTL_PCI_AD12		0x140
-#define IOCTL_PCI_AD11		0x144
-#define IOCTL_PCI_AD10		0x148
-#define IOCTL_PCI_AD09		0x14C
-#define IOCTL_PCI_AD08		0x150
-#define IOCTL_PCI_AD07		0x154
-#define IOCTL_PCI_AD06		0x158
-#define IOCTL_PCI_AD05		0x15C
-#define IOCTL_PCI_AD04		0x160
-#define IOCTL_PCI_AD03		0x164
-#define IOCTL_PCI_AD02		0x168
-#define IOCTL_PCI_AD01		0x16C
-#define IOCTL_PCI_AD00		0x170
-#define IOCTL_PCI_CBE0		0x174
-#define IOCTL_PCI_CBE1		0x178
-#define IOCTL_PCI_CBE2		0x17C
-#define IOCTL_PCI_CBE3		0x180
-#define IOCTL_PCI_GNT2		0x184
-#define IOCTL_PCI_REQ2		0x188
-#define IOCTL_PCI_GNT1		0x18C
-#define IOCTL_PCI_REQ1		0x190
-#define IOCTL_PCI_GNT0		0x194
-#define IOCTL_PCI_REQ0		0x198
-#define IOCTL_PCI_INTA		0x19C
-#define IOCTL_PCI_CLK		0x1A0
-#define IOCTL_PCI_RST_OUT	0x1A4
-#define IOCTL_PCI_FRAME		0x1A8
-#define IOCTL_PCI_IDSEL		0x1AC
-#define IOCTL_PCI_DEVSEL	0x1B0
-#define IOCTL_PCI_IRDY		0x1B4
-#define IOCTL_PCI_TRDY		0x1B8
-#define IOCTL_PCI_STOP		0x1BC
-#define IOCTL_PCI_PAR		0x1C0
-#define IOCTL_PCI_PERR		0x1C4
-#define IOCTL_PCI_SERR		0x1C8
-#define IOCTL_SPDIF_TXCLK	0x1CC
-#define IOCTL_SPDIF_TX		0x1D0
-#define IOCTL_SPDIF_RX		0x1D4
-#define IOCTL_I2C0_SCL		0x1D8
-#define IOCTL_I2C0_SDA		0x1DC
-#define IOCTL_I2C1_SCL		0x1E0
-#define IOCTL_I2C1_SDA		0x1E4
-#define IOCTL_I2C2_SCL		0x1E8
-#define IOCTL_I2C2_SDA		0x1EC
-#define IOCTL_IRQ0		0x1F0
-#define IOCTL_IRQ1		0x1F4
-#define IOCTL_CAN1_TX		0x1F8
-#define IOCTL_CAN2_TX		0x1FC
-#define IOCTL_J1850_TX		0x200
-#define IOCTL_J1850_RX		0x204
-#define IOCTL_PSC_MCLK_IN	0x208
-#define IOCTL_PSC0_0		0x20C
-#define IOCTL_PSC0_1		0x210
-#define IOCTL_PSC0_2		0x214
-#define IOCTL_PSC0_3		0x218
-#define IOCTL_PSC0_4		0x21C
-#define IOCTL_PSC1_0		0x220
-#define IOCTL_PSC1_1		0x224
-#define IOCTL_PSC1_2		0x228
-#define IOCTL_PSC1_3		0x22C
-#define IOCTL_PSC1_4		0x230
-#define IOCTL_PSC2_0		0x234
-#define IOCTL_PSC2_1		0x238
-#define IOCTL_PSC2_2		0x23C
-#define IOCTL_PSC2_3		0x240
-#define IOCTL_PSC2_4		0x244
-#define IOCTL_PSC3_0		0x248
-#define IOCTL_PSC3_1		0x24C
-#define IOCTL_PSC3_2		0x250
-#define IOCTL_PSC3_3		0x254
-#define IOCTL_PSC3_4		0x258
-#define IOCTL_PSC4_0		0x25C
-#define IOCTL_PSC4_1		0x260
-#define IOCTL_PSC4_2		0x264
-#define IOCTL_PSC4_3		0x268
-#define IOCTL_PSC4_4		0x26C
-#define IOCTL_PSC5_0		0x270
-#define IOCTL_PSC5_1		0x274
-#define IOCTL_PSC5_2		0x278
-#define IOCTL_PSC5_3		0x27C
-#define IOCTL_PSC5_4		0x280
-#define IOCTL_PSC6_0		0x284
-#define IOCTL_PSC6_1		0x288
-#define IOCTL_PSC6_2		0x28C
-#define IOCTL_PSC6_3		0x290
-#define IOCTL_PSC6_4		0x294
-#define IOCTL_PSC7_0		0x298
-#define IOCTL_PSC7_1		0x29C
-#define IOCTL_PSC7_2		0x2A0
-#define IOCTL_PSC7_3		0x2A4
-#define IOCTL_PSC7_4		0x2A8
-#define IOCTL_PSC8_0		0x2AC
-#define IOCTL_PSC8_1		0x2B0
-#define IOCTL_PSC8_2		0x2B4
-#define IOCTL_PSC8_3		0x2B8
-#define IOCTL_PSC8_4		0x2BC
-#define IOCTL_PSC9_0		0x2C0
-#define IOCTL_PSC9_1		0x2C4
-#define IOCTL_PSC9_2		0x2C8
-#define IOCTL_PSC9_3		0x2CC
-#define IOCTL_PSC9_4		0x2D0
-#define IOCTL_PSC10_0		0x2D4
-#define IOCTL_PSC10_1		0x2D8
-#define IOCTL_PSC10_2		0x2DC
-#define IOCTL_PSC10_3		0x2E0
-#define IOCTL_PSC10_4		0x2E4
-#define IOCTL_PSC11_0		0x2E8
-#define IOCTL_PSC11_1		0x2EC
-#define IOCTL_PSC11_2		0x2F0
-#define IOCTL_PSC11_3		0x2F4
-#define IOCTL_PSC11_4		0x2F8
-#define IOCTL_HRESET		0x2FC
-#define IOCTL_SRESET		0x300
-#define IOCTL_CKSTP_OUT		0x304
-#define IOCTL_USB2_VBUS_PWR_FAULT	0x308
-#define IOCTL_USB2_VBUS_PWR_SELECT	0x30C
-#define IOCTL_USB2_PHY_DRVV_BUS		0x310
-
-extern void iopin_initialize(void);
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index f2bed5c..08d89d7 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -349,7 +349,7 @@ int is_pci_host(struct pci_controller *hose)
 	return 1;
 }
 
-int katmai_pcie_card_present(int port)
+static int katmai_pcie_card_present(int port)
 {
 	u32 val;
 
@@ -437,76 +437,6 @@ void pcie_setup_hoses(int busno)
 }
 #endif	/* defined(CONFIG_PCI) */
 
-int misc_init_f (void)
-{
-	uint reg;
-#if defined(CONFIG_STRESS)
-	uint i ;
-	uint disp;
-#endif
-
-	/* minimal init for PCIe */
-#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
-	/* pci express 0 Endpoint Mode */
-	mfsdr(SDR0_PE0DLPSET, reg);
-	reg &= (~0x00400000);
-	mtsdr(SDR0_PE0DLPSET, reg);
-#else
-	/* pci express 0 Rootpoint  Mode */
-	mfsdr(SDR0_PE0DLPSET, reg);
-	reg |= 0x00400000;
-	mtsdr(SDR0_PE0DLPSET, reg);
-#endif
-	/* pci express 1 Rootpoint  Mode */
-	mfsdr(SDR0_PE1DLPSET, reg);
-	reg |= 0x00400000;
-	mtsdr(SDR0_PE1DLPSET, reg);
-	/* pci express 2 Rootpoint  Mode */
-	mfsdr(SDR0_PE2DLPSET, reg);
-	reg |= 0x00400000;
-	mtsdr(SDR0_PE2DLPSET, reg);
-
-#if defined(CONFIG_STRESS)
-	/*
-	 * All this setting done by linux only needed by stress an charac. test
-	 * procedure
-	 * PCIe 1 Rootpoint PCIe2 Endpoint
-	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
-	 */
-	for (i=0,disp=0; i<8; i++,disp+=3) {
-		mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
-	}
-
-	/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
-	for (i=0,disp=0; i<4; i++,disp+=3) {
-		mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
-	}
-
-	/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
-	for (i=0,disp=0; i<4; i++,disp+=3) {
-		mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
-	}
-
-	reg = 0x21242222;
-	mtsdr(SDR0_PE2UTLSET1, reg);
-	reg = 0x11000000;
-	mtsdr(SDR0_PE2UTLSET2, reg);
-	/* pci express 1 Endpoint  Mode */
-	reg = 0x00004000;
-	mtsdr(SDR0_PE2DLPSET, reg);
-
-	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
-#endif
-
-	return 0;
-}
-
 #ifdef CONFIG_POST
 /*
  * Returns 1 if keys pressed to start the power-on long-running tests
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index eea1e1e..4d1d093 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -147,36 +147,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic1pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x01c00008);	/* per ref-board manual */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000); /* clear all */
-	mtdcr (uicb0er, 0x00000000); /* disable all */
-	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000); /* */
-	mtdcr (uicb0tr, 0x00000000); /* */
-	mtdcr (uicb0vr, 0x00000001); /* */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000); /* clear all */
+	mtdcr (uic0er, 0x00000000); /* disable all */
+	mtdcr (uic0cr, 0x00000000); /* all non-critical */
+	mtdcr (uic0pr, 0xfc000000); /* */
+	mtdcr (uic0tr, 0x00000000); /* */
+	mtdcr (uic0vr, 0x00000001); /* */
 	mfsdr (sdr_mfr, mfr);
 	mfr &= ~SDR0_MFR_ECS_MASK;
 /*	mtsdr(sdr_mfr, mfr); */
diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile
new file mode 100644
index 0000000..5793307
--- /dev/null
+++ b/board/amcc/redwood/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk
new file mode 100644
index 0000000..f33336d
--- /dev/null
+++ b/board/amcc/redwood/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 460SX Reference Platform (redwood) board
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xfffb0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S
new file mode 100644
index 0000000..fcffada
--- /dev/null
+++ b/board/amcc/redwood/init.S
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	/* Although 512 KB, map 256k at a time */
+	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CFG_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+
+	tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/*
+	 * Peripheral base
+	 */
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end
diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
new file mode 100644
index 0000000..37a0c31
--- /dev/null
+++ b/board/amcc/redwood/redwood.c
@@ -0,0 +1,456 @@
+/*
+ * This is the main board level file for the Redwood AMCC board.
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include "redwood.h"
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <asm-ppc/io.h>
+
+int compare_to_true(char *str);
+char *remove_l_w_space(char *in_str);
+char *remove_t_w_space(char *in_str);
+int get_console_port(void);
+
+static void early_init_EBC(void);
+static int bootdevice_selected(void);
+static void early_reinit_EBC(int);
+static void early_init_UIC(void);
+
+/*
+ * Define Boot devices
+ */
+#define BOOT_FROM_8BIT_SRAM			0x00
+#define BOOT_FROM_16BIT_SRAM			0x01
+#define BOOT_FROM_32BIT_SRAM			0x02
+#define BOOT_FROM_8BIT_NAND			0x03
+#define BOOT_FROM_16BIT_NOR			0x04
+#define BOOT_DEVICE_UNKNOWN			0xff
+
+/*
+ * EBC Devices Characteristics
+ *   Peripheral Bank Access Parameters       -   EBC_BxAP
+ *   Peripheral Bank Configuration Register  -   EBC_BxCR
+ */
+
+/*
+ * 8 bit width SRAM
+ * BU Value
+ * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_8BIT_SRAM					\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXAP_16BIT_SRAM	EBC_BXAP_8BIT_SRAM
+#define EBC_BXAP_32BIT_SRAM	EBC_BXAP_8BIT_SRAM
+
+/*
+ * NAND flash
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NAND						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+/*
+ * NOR flash
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NOR						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(11) |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1)  |	\
+	EBC_BXAP_WBN_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(1)  |	\
+	EBC_BXAP_TH_ENCODE(1)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_RW         |	\
+	EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_8BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_32BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_NAND_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_16BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS1						\
+	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NAND_CS1						\
+	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_NAND_CS2						\
+	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SRAM_CS2						\
+	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2					\
+	EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_FPGA_CS3						\
+	EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+/*****************************************************************************
+ * UBOOT initiated board specific function calls
+ ****************************************************************************/
+
+int board_early_init_f(void)
+{
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*
+	 * Initialise EBC
+	 */
+	early_init_EBC();
+
+	/*
+	 * Determine which boot device was selected
+	 */
+	computed_boot_device = bootdevice_selected();
+
+	/*
+	 * Reinit EBC based on selected boot device
+	 */
+	early_reinit_EBC(computed_boot_device);
+
+	/*
+	 * Setup for UIC on 460SX redwood board
+	 */
+	early_init_UIC();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Redwood - AMCC 460SX Reference Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+static void early_init_EBC(void)
+{
+	/*
+	 * Initialize EBC CONFIG -
+	 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+	 * default value :
+	 *      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+	 */
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_16PERCLK |
+	      EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_OEO_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
+
+	/*
+	 * PART 1 : Initialize EBC Bank 3
+	 * ==============================
+	 * Bank1 is always associated to the EPLD.
+	 * It has to be initialized prior to other banks settings computation
+	 * since some board registers values may be needed to determine the
+	 * boot type
+	 */
+	mtebc(pb1ap, EBC_BXAP_FPGA);
+	mtebc(pb1cr, EBC_BXCR_FPGA_CS3);
+
+}
+
+static int bootdevice_selected(void)
+{
+	unsigned long sdr0_pinstp;
+	unsigned long bootstrap_settings;
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*
+	 *  Determine which boot device was selected
+	 *  =================================================
+	 *
+	 *  Read Pin Strap Register in PPC460SX
+	 *  Result can either be :
+	 *   - Boot strap = boot from EBC 8bits     => Small Flash
+	 *   - Boot strap = boot from PCI
+	 *   - Boot strap = IIC
+	 *  In case of boot from IIC, read Serial Device Strap Register1
+	 *
+	 *  Result can either be :
+	 *   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
+	 *   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
+	 *   - Boot from PCI
+	 */
+
+	/* Read Pin Strap Register in PPC460SX */
+	mfsdr(SDR0_PINSTP, sdr0_pinstp);
+	bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+	switch (bootstrap_settings) {
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+		/*
+		 * Boot from SRAM, 8bit width
+		 */
+		computed_boot_device = BOOT_FROM_8BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+		/*
+		 * Boot from SRAM, 32bit width
+		 */
+		computed_boot_device = BOOT_FROM_32BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+		/*
+		 * Boot from NAND, 8bit width
+		 */
+		computed_boot_device = BOOT_FROM_8BIT_NAND;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+		/*
+		 * Boot from SRAM, 16bit width
+		 * Boot setting in IIC EEPROM 0x50
+		 */
+		computed_boot_device = BOOT_FROM_16BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
+		/*
+		 * Boot from NOR, 16bit width
+		 * Boot setting in IIC EEPROM 0x54
+		 */
+		computed_boot_device = BOOT_FROM_16BIT_NOR;
+		break;
+	default:
+		/* should not be */
+		computed_boot_device = BOOT_DEVICE_UNKNOWN;
+		break;
+	}
+
+	return computed_boot_device;
+}
+
+static void early_reinit_EBC(int computed_boot_device)
+{
+	/*
+	 *  Compute EBC settings depending on selected boot device
+	 *  ======================================================
+	 *
+	 * Resulting EBC init will be among following configurations :
+	 *
+	 *  - Boot from EBC 8bits => boot from Small Flash selected
+	 *            EBC-CS0     = Small Flash
+	 *            EBC-CS2     = Large Flash and SRAM
+	 *
+	 *  - Boot from EBC 16bits => boot from Large Flash or SRAM
+	 *            EBC-CS0     = Large Flash or SRAM
+	 *            EBC-CS2     = Small Flash
+	 *
+	 *  - Boot from PCI
+	 *            EBC-CS0     = not initialized to avoid address contention
+	 *            EBC-CS2     = same as boot from Small Flash selected
+	 */
+
+	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+	unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
+	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+	switch (computed_boot_device) {
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_8BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_16BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_32BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_16BIT_NOR:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_8BIT_NAND:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	default:
+		/*-------------------------------------------------------------------*/
+		/* BOOT_DEVICE_UNKNOWN */
+		break;
+	}
+
+	mtebc(pb0ap, ebc0_cs0_bxap_value);
+	mtebc(pb0cr, ebc0_cs0_bxcr_value);
+	mtebc(pb1ap, ebc0_cs1_bxap_value);
+	mtebc(pb1cr, ebc0_cs1_bxcr_value);
+	mtebc(pb2ap, ebc0_cs2_bxap_value);
+	mtebc(pb2cr, ebc0_cs2_bxcr_value);
+}
+
+static void early_init_UIC(void)
+{
+	/*
+	 * Initialise UIC registers.  Clear all interrupts.  Disable all
+	 * interrupts.
+	 * Set critical interrupt values.  Set interrupt polarities.  Set
+	 * interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 * interrupts again.
+	 */
+	mtdcr(uic3sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic3er, 0x00000000);	/* disable all interrupts */
+	mtdcr(uic3cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic3pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic3sr, 0xffffffff);	/* clear all  interrupts */
+
+	mtdcr(uic2sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic2er, 0x00000000);	/* disable all interrupts */
+	mtdcr(uic2cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic2pr, 0xebebebff);	/* Set Interrupt Polarities */
+	mtdcr(uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic2sr, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(uic1sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic1er, 0x00000000);	/* disable all interrupts */
+	mtdcr(uic1cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(uic1tr, 0x001fc0ff);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(uic0sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic0er, 0x00000000);	/* disable all interrupts excepted
+					 * cascade to be checked */
+	mtdcr(uic0cr, 0x00104001);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic0pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(uic0tr, 0x000f003c);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all interrupts */
+
+}
diff --git a/board/amcc/redwood/redwood.h b/board/amcc/redwood/redwood.h
new file mode 100644
index 0000000..89b87e6
--- /dev/null
+++ b/board/amcc/redwood/redwood.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __REDWOOD_H_
+#define __REDWOOD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+/* Pin Straps Reg */
+#define SDR0_PSTRP0			0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000	/* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000	/* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000	/* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000	/* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000	/* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000	/* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000	/* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000	/* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000	/* Default strap settings 7 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* __REDWOOD_H_ */
diff --git a/board/amcc/redwood/u-boot.lds b/board/amcc/redwood/u-boot.lds
new file mode 100644
index 0000000..2104cc2
--- /dev/null
+++ b/board/amcc/redwood/u-boot.lds
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o		(.text)
+    board/amcc/redwood/init.o	(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index b833092..176d5cf 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -25,12 +25,11 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-#include <ppc440.h>
+#include <ppc4xx.h>
 #include <asm/gpio.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/bitops.h>
-#include <asm/ppc4xx-intvec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,6 +92,11 @@ int board_early_init_f(void)
 #ifdef CONFIG_I2C_MULTI_BUS
 	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
 #endif
+	/* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
+
 	mfsdr(SDR0_PFC2, sdr0_pfc2);
 	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 		SDR0_PFC2_SELECT_CONFIG_4;
@@ -335,7 +339,7 @@ int checkboard(void)
  */
 void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
 }
 #endif
 
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index b6c3065..fdd82e7 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -119,36 +119,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic1pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x01c00008);	/* per ref-board manual */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
-	mtdcr (uicb0er, 0x00000000);	/* disable all */
-	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000);	/* */
-	mtdcr (uicb0tr, 0x00000000);	/* */
-	mtdcr (uicb0vr, 0x00000001);	/* */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic0pr, 0xfc000000);	/* */
+	mtdcr (uic0tr, 0x00000000);	/* */
+	mtdcr (uic0vr, 0x00000001);	/* */
 
 	/* Enable two GPIO 10~11 and TraceA signal */
 	mfsdr(sdr_pfc0,reg);
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 6608893..84c3938 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -677,7 +677,7 @@ int is_pci_host(struct pci_controller *hose)
 	return 1;
 }
 
-int yucca_pcie_card_present(int port)
+static int yucca_pcie_card_present(int port)
 {
 	u16 reg;
 
@@ -879,10 +879,6 @@ void pcie_setup_hoses(int busno)
 int misc_init_f (void)
 {
 	uint reg;
-#if defined(CONFIG_STRESS)
-	uint i ;
-	uint disp;
-#endif
 
 	out16(FPGA_REG10, (in16(FPGA_REG10) &
 			~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
@@ -897,67 +893,23 @@ int misc_init_f (void)
 
 	/* minimal init for PCIe */
 	/* pci express 0 Endpoint Mode */
-	mfsdr(SDR0_PE0DLPSET, reg);
+	mfsdr(SDRN_PESDR_DLPSET(0), reg);
 	reg &= (~0x00400000);
-	mtsdr(SDR0_PE0DLPSET, reg);
+	mtsdr(SDRN_PESDR_DLPSET(0), reg);
 	/* pci express 1 Rootpoint  Mode */
-	mfsdr(SDR0_PE1DLPSET, reg);
+	mfsdr(SDRN_PESDR_DLPSET(1), reg);
 	reg |= 0x00400000;
-	mtsdr(SDR0_PE1DLPSET, reg);
+	mtsdr(SDRN_PESDR_DLPSET(1), reg);
 	/* pci express 2 Rootpoint  Mode */
-	mfsdr(SDR0_PE2DLPSET, reg);
+	mfsdr(SDRN_PESDR_DLPSET(2), reg);
 	reg |= 0x00400000;
-	mtsdr(SDR0_PE2DLPSET, reg);
+	mtsdr(SDRN_PESDR_DLPSET(2), reg);
 
 	out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
 				~FPGA_REG1C_PE0_ROOTPOINT &
 				~FPGA_REG1C_PE1_ENDPOINT  &
 				~FPGA_REG1C_PE2_ENDPOINT));
 
-#if defined(CONFIG_STRESS)
-	/*
-	 * all this setting done by linux only needed by stress an charac. test
-	 * procedure
-	 * PCIe 1 Rootpoint PCIe2 Endpoint
-	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-	 * Power Level
-	 */
-	for (i = 0, disp = 0; i < 8; i++, disp += 3) {
-		mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
-	}
-
-	/*
-	 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-	 * Power Level
-	 */
-	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
-		mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
-	}
-
-	/*
-	 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-	 * Power Level
-	 */
-	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
-		mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
-	}
-
-	reg = 0x21242222;
-	mtsdr(SDR0_PE2UTLSET1, reg);
-	reg = 0x11000000;
-	mtsdr(SDR0_PE2UTLSET2, reg);
-	/* pci express 1 Endpoint  Mode */
-	reg = 0x00004000;
-	mtsdr(SDR0_PE2DLPSET, reg);
-
-	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
-#endif
 	return 0;
 }
 
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
index 6ff0f4f..9800083 100644
--- a/board/bf537-stamp/nand.c
+++ b/board/bf537-stamp/nand.c
@@ -37,34 +37,29 @@
 /*
  * hardware specific access to control-lines
  */
-static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
+static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	register struct nand_chip *this = mtd->priv;
+	u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
 
-	switch (cmd) {
-
-	case NAND_CTL_SETCLE:
-		this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
-		break;
-	case NAND_CTL_CLRCLE:
-		this->IO_ADDR_W = CFG_NAND_BASE;
-		break;
-
-	case NAND_CTL_SETALE:
-		this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
-		break;
-	case NAND_CTL_CLRALE:
-		this->IO_ADDR_W = CFG_NAND_BASE;
-		break;
-	case NAND_CTL_SETNCE:
-	case NAND_CTL_CLRNCE:
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if( ctrl & NAND_CLE )
+			IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
+		else
+			IO_ADDR_W = CFG_NAND_BASE;
+		if( ctrl & NAND_ALE )
+			IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
+		else
+			IO_ADDR_W = CFG_NAND_BASE;
+		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
 	}
-
 	this->IO_ADDR_R = this->IO_ADDR_W;
 
 	/* Drain the writebuffer */
 	SSYNC();
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 int bfin_device_ready(struct mtd_info *mtd)
@@ -79,11 +74,11 @@ int bfin_device_ready(struct mtd_info *mtd)
  * argument are board-specific (per include/linux/mtd/nand.h):
  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -98,8 +93,8 @@ void board_nand_init(struct nand_chip *nand)
 	*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
 	*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
 
-	nand->hwcontrol = bfin_hwcontrol;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = bfin_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->dev_ready = bfin_device_ready;
 	nand->chip_delay = 30;
 }
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
index 09c0b04..3ccbf65 100644
--- a/board/dave/PPChameleonEVB/nand.c
+++ b/board/dave/PPChameleonEVB/nand.c
@@ -21,7 +21,7 @@
  */
 
 #include <common.h>
-
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NAND)
 
@@ -31,31 +31,28 @@
  * hardware specific access to control-lines
  * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
  */
-static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd->priv;
 	ulong base = (ulong) this->IO_ADDR_W;
 
-	switch(cmd) {
-	case NAND_CTL_SETCLE:
-		MACRO_NAND_CTL_SETCLE((unsigned long)base);
-		break;
-	case NAND_CTL_CLRCLE:
-		MACRO_NAND_CTL_CLRCLE((unsigned long)base);
-		break;
-	case NAND_CTL_SETALE:
-		MACRO_NAND_CTL_SETALE((unsigned long)base);
-		break;
-	case NAND_CTL_CLRALE:
-		MACRO_NAND_CTL_CLRALE((unsigned long)base);
-		break;
-	case NAND_CTL_SETNCE:
-		MACRO_NAND_ENABLE_CE((unsigned long)base);
-		break;
-	case NAND_CTL_CLRNCE:
-		MACRO_NAND_DISABLE_CE((unsigned long)base);
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			MACRO_NAND_CTL_SETCLE((unsigned long)base);
+		else
+			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+		if ( ctrl & NAND_ALE )
+			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+		else
+			MACRO_NAND_CTL_CLRALE((unsigned long)base);
+		if ( ctrl & NAND_NCE )
+			MACRO_NAND_ENABLE_CE((unsigned long)base);
+		else
+			MACRO_NAND_DISABLE_CE((unsigned long)base);
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 
@@ -92,11 +89,11 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
  * argument are board-specific (per include/linux/mtd/nand.h):
  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -108,9 +105,9 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
 int board_nand_init(struct nand_chip *nand)
 {
 
-	nand->hwcontrol = ppchameleonevb_hwcontrol;
+	nand->cmd_ctrl = ppchameleonevb_hwcontrol;
 	nand->dev_ready = ppchameleonevb_device_ready;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->chip_delay = NAND_BIG_DELAY_US;
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	return 0;
diff --git a/board/delta/nand.c b/board/delta/nand.c
index 5024056..4ce78a1 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -23,7 +23,7 @@
 #include <common.h>
 
 #if defined(CONFIG_CMD_NAND)
-#if !defined(CFG_NAND_LEGACY)
+#if !defined(CONFIG_NAND_LEGACY)
 
 #include <nand.h>
 #include <asm/arch/pxa-regs.h>
@@ -69,7 +69,7 @@ static struct nand_oobinfo delta_oob = {
 /*
  * not required for Monahans DFC
  */
-static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	return;
 }
@@ -110,30 +110,6 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 }
 
 
-/*
- * These functions are quite problematic for the DFC. Luckily they are
- * not used in the current nand code, except for nand_command, which
- * we've defined our own anyway. The problem is, that we always need
- * to write 4 bytes to the DFC Data Buffer, but in these functions we
- * don't know if to buffer the bytes/half words until we've gathered 4
- * bytes or if to send them straight away.
- *
- * Solution: Don't use these with Mona's DFC and complain loudly.
- */
-static void dfc_write_word(struct mtd_info *mtd, u16 word)
-{
-	printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
-}
-static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
-{
-	printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
-}
-
-/* The original:
- * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
- *
- * Shouldn't this be "u_char * const buf" ?
- */
 static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
 {
 	int i=0, j;
@@ -168,7 +144,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
  */
 static u16 dfc_read_word(struct mtd_info *mtd)
 {
-	printf("dfc_write_byte: UNIMPLEMENTED.\n");
+	printf("dfc_read_word: UNIMPLEMENTED.\n");
 	return 0;
 }
 
@@ -289,9 +265,10 @@ static void dfc_new_cmd(void)
 
 /* this function is called after Programm and Erase Operations to
  * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
 {
 	unsigned long ndsr=0, event=0;
+	int state = this->state;
 
 	if(state == FL_WRITING) {
 		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
@@ -439,7 +416,7 @@ static void dfc_gpio_init(void)
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -561,20 +538,18 @@ int board_nand_init(struct nand_chip *nand)
 	/*	wait(10); */
 
 
-	nand->hwcontrol = dfc_hwcontrol;
+	nand->cmd_ctrl = dfc_hwcontrol;
 /*	nand->dev_ready = dfc_device_ready; */
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->options = NAND_BUSWIDTH_16;
 	nand->waitfunc = dfc_wait;
 	nand->read_byte = dfc_read_byte;
-	nand->write_byte = dfc_write_byte;
 	nand->read_word = dfc_read_word;
-	nand->write_word = dfc_write_word;
 	nand->read_buf = dfc_read_buf;
 	nand->write_buf = dfc_write_buf;
 
 	nand->cmdfunc = dfc_cmdfunc;
-	nand->autooob = &delta_oob;
+/*	nand->autooob = &delta_oob; */
 	nand->badblock_pattern = &delta_bbt_descr;
 	return 0;
 }
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index 7e6eea0..a1e0ce5 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -27,7 +27,7 @@
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
-#if defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_NAND_LEGACY)
 #include <linux/mtd/nand_legacy.h>
 #endif
 #include <fat.h>
@@ -58,7 +58,7 @@ extern int flash_sect_erase(ulong, ulong);
 extern int flash_sect_protect (int, ulong, ulong);
 extern int flash_write (char *, ulong, ulong);
 
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 /* references to names in cmd_nand.c */
 #define NANDRW_READ	0x01
 #define NANDRW_WRITE	0x00
@@ -158,7 +158,7 @@ int au_do_update(int i, long sz)
 	int off, rc;
 	uint nbytes;
 	int k;
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 	int total;
 #endif
 
@@ -241,7 +241,7 @@ int au_do_update(int i, long sz)
 			debug ("flash_sect_erase(%lx, %lx);\n", start, end);
 			flash_sect_erase (start, end);
 		} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 			printf ("Updating NAND FLASH with image %s\n",
 				au_image[i].name);
 			debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
@@ -273,7 +273,7 @@ int au_do_update(int i, long sz)
 			rc = flash_write ((char *)addr, start,
 					  (nbytes + 1) & ~1);
 		} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 			debug ("nand_legacy_rw(%p, %lx, %x)\n",
 			       addr, start, nbytes);
 			rc = nand_legacy_rw (nand_dev_desc,
@@ -298,7 +298,7 @@ int au_do_update(int i, long sz)
 			rc = crc32 (0, (uchar *)(start + off),
 				    image_get_data_size (hdr));
 		} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 			rc = nand_legacy_rw (nand_dev_desc,
 					     NANDRW_READ | NANDRW_JFFS2 |
 					     NANDRW_JFFS2_SKIP,
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
index 7bf6847..40d1efb 100644
--- a/board/esd/common/esd405ep_nand.c
+++ b/board/esd/common/esd405ep_nand.c
@@ -30,28 +30,26 @@
 /*
  * hardware specific access to control-lines
  */
-static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	switch(cmd) {
-	case NAND_CTL_SETCLE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
-		break;
-	case NAND_CTL_CLRCLE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
-		break;
-	case NAND_CTL_SETALE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
-		break;
-	case NAND_CTL_CLRALE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
-		break;
-	case NAND_CTL_SETNCE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
-		break;
-	case NAND_CTL_CLRNCE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
-		break;
+	struct nand_chip *this = mtd->priv;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+		if ( ctrl & NAND_ALE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+		if ( ctrl & NAND_NCE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 
@@ -77,9 +75,9 @@ int board_nand_init(struct nand_chip *nand)
 	/*
 	 * Initialize nand_chip structure
 	 */
-	nand->hwcontrol = esd405ep_nand_hwcontrol;
+	nand->cmd_ctrl = esd405ep_nand_hwcontrol;
 	nand->dev_ready = esd405ep_nand_device_ready;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->chip_delay = NAND_BIG_DELAY_US;
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	return 0;
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 344a614..f84912e 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -40,36 +40,26 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SET_ALE		0x08
 #define CLR_ALE		~SET_ALE
 
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtdinfo->priv;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+/*	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
 	u32 nand_baseaddr = (u32) this->IO_ADDR_W;
 
-	switch (cmd) {
-	case NAND_CTL_SETNCE:
-	case NAND_CTL_CLRNCE:
-		break;
-	case NAND_CTL_SETCLE:
-		nand_baseaddr |= SET_CLE;
-		break;
-	case NAND_CTL_CLRCLE:
-		nand_baseaddr &= CLR_CLE;
-		break;
-	case NAND_CTL_SETALE:
-		nand_baseaddr |= SET_ALE;
-		break;
-	case NAND_CTL_CLRALE:
-		nand_baseaddr |= CLR_ALE;
-		break;
-	case NAND_CTL_SETWP:
-		fbcs->csmr2 |= FBCS_CSMR_WP;
-		break;
-	case NAND_CTL_CLRWP:
-		fbcs->csmr2 &= ~FBCS_CSMR_WP;
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			nand_baseaddr |= SET_CLE;
+		else
+			nand_baseaddr &= CLR_CLE;
+		if ( ctrl & NAND_ALE )
+			nand_baseaddr |= SET_ALE;
+		else
+			nand_baseaddr &= CLR_ALE;
 	}
 	this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
@@ -103,8 +93,8 @@ int board_nand_init(struct nand_chip *nand)
 	gpio->podr_timer = 0;
 
 	nand->chip_delay = 50;
-	nand->eccmode = NAND_ECC_SOFT;
-	nand->hwcontrol = nand_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_hwcontrol;
 	nand->read_byte = nand_read_byte;
 	nand->write_byte = nand_write_byte;
 	nand->dev_ready = nand_dev_ready;
diff --git a/board/freescale/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk
index f768264..fd72a14 100644
--- a/board/freescale/mpc8313erdb/config.mk
+++ b/board/freescale/mpc8313erdb/config.mk
@@ -1 +1,7 @@
+ifndef NAND_SPL
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+endif
+
+ifndef TEXT_BASE
 TEXT_BASE = 0xFE000000
+endif
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 7cbdb7b..ebb703d 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -29,6 +29,8 @@
 #include <pci.h>
 #include <mpc83xx.h>
 #include <vsc7385.h>
+#include <ns16550.h>
+#include <nand.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +52,7 @@ int checkboard(void)
 	return 0;
 }
 
+#ifndef CONFIG_NAND_SPL
 static struct pci_region pci_regions[] = {
 	{
 		bus_start: CFG_PCI1_MEM_BASE,
@@ -128,3 +131,32 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 }
 #endif
+#else /* CONFIG_NAND_SPL */
+void board_init_f(ulong bootflag)
+{
+	board_early_init_f();
+	NS16550_init((NS16550_t)(CFG_IMMR + 0x4500),
+	             CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	puts("NAND boot... ");
+	init_timebase();
+	initdram(0);
+	relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+	              CFG_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (gd->flags & GD_FLG_SILENT)
+		return;
+
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c);
+}
+#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index afd8b9d..3a6347f 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -58,8 +58,10 @@ static void resume_from_sleep(void)
  */
 static long fixed_sdram(void)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+
+#ifndef CFG_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
 	u32 msize_log2 = __ilog2(msize);
 
 	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
@@ -100,6 +102,7 @@ static long fixed_sdram(void)
 
 	/* enable DDR controller */
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+#endif
 
 	return msize;
 }
diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds
index 0e4f5a2..515d320 100644
--- a/board/freescale/mpc8540ads/u-boot.lds
+++ b/board/freescale/mpc8540ads/u-boot.lds
@@ -26,6 +26,12 @@
 OUTPUT_ARCH(powerpc)
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -57,7 +63,7 @@ SECTIONS
     *(.text)
     *(.fixup)
     *(.got1)
-   }
+   } :text
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
@@ -66,7 +72,7 @@ SECTIONS
     *(.rodata1)
     *(.rodata.str1.4)
     *(.eh_frame)
-  }
+  } :text
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
@@ -118,12 +124,12 @@ SECTIONS
   .bootpg ADDR(.text) + 0x7f000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
+  } :text = 0xffff
 
   .resetvec ADDR(.text) + 0x7fffc :
   {
     *(.resetvec)
-  } = 0xffff
+  } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
 
@@ -134,7 +140,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
-  }
+  } :bss
 
   . = ALIGN(4);
   _end = . ;
diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds
index 1c583de..d728d8b 100644
--- a/board/freescale/mpc8541cds/u-boot.lds
+++ b/board/freescale/mpc8541cds/u-boot.lds
@@ -23,6 +23,12 @@
 OUTPUT_ARCH(powerpc)
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
     *(.text)
     *(.fixup)
     *(.got1)
-   }
+   } :text
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
@@ -63,7 +69,7 @@ SECTIONS
     *(.rodata1)
     *(.rodata.str1.4)
     *(.eh_frame)
-  }
+  } :text
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
@@ -115,12 +121,12 @@ SECTIONS
   .bootpg ADDR(.text) + 0x7f000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
+  } :text = 0xffff
 
   .resetvec ADDR(.text) + 0x7fffc :
   {
     *(.resetvec)
-  } = 0xffff
+  } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
 
@@ -131,7 +137,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
-  }
+  } :bss
 
   . = ALIGN(4);
   _end = . ;
diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds
index 500e647..a05ece5 100644
--- a/board/freescale/mpc8544ds/u-boot.lds
+++ b/board/freescale/mpc8544ds/u-boot.lds
@@ -23,6 +23,12 @@
 OUTPUT_ARCH(powerpc)
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
     *(.text)
     *(.fixup)
     *(.got1)
-   }
+   } :text
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
@@ -63,7 +69,7 @@ SECTIONS
     *(.rodata1)
     *(.rodata.str1.4)
     *(.eh_frame)
-  }
+  } :text
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
@@ -115,12 +121,12 @@ SECTIONS
   .bootpg ADDR(.text) + 0x7f000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
+  } :text = 0xffff
 
   .resetvec ADDR(.text) + 0x7fffc :
   {
     *(.resetvec)
-  } = 0xffff
+  } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
 
@@ -131,7 +137,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
-  }
+  } :bss
 
   . = ALIGN(4);
   _end = . ;
diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds
index 6b93395..d4a2f72 100644
--- a/board/freescale/mpc8548cds/u-boot.lds
+++ b/board/freescale/mpc8548cds/u-boot.lds
@@ -23,6 +23,12 @@
 OUTPUT_ARCH(powerpc)
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
     *(.text)
     *(.fixup)
     *(.got1)
-   }
+   } :text
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
@@ -63,7 +69,7 @@ SECTIONS
     *(.rodata1)
     *(.rodata.str1.4)
     *(.eh_frame)
-  }
+  } :text
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
@@ -115,12 +121,12 @@ SECTIONS
   .bootpg ADDR(.text) + 0x7f000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
+  } :text = 0xffff
 
   .resetvec ADDR(.text) + 0x7fffc :
   {
     *(.resetvec)
-  } = 0xffff
+  } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
 
@@ -131,7 +137,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
-  }
+  } :bss
 
   . = ALIGN(4);
   _end = . ;
diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds
index a18b3a7..11885e8 100644
--- a/board/freescale/mpc8555cds/u-boot.lds
+++ b/board/freescale/mpc8555cds/u-boot.lds
@@ -23,6 +23,12 @@
 OUTPUT_ARCH(powerpc)
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
     *(.text)
     *(.fixup)
     *(.got1)
-   }
+   } :text
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
@@ -63,7 +69,7 @@ SECTIONS
     *(.rodata1)
     *(.rodata.str1.4)
     *(.eh_frame)
-  }
+  } :text
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
@@ -115,12 +121,12 @@ SECTIONS
   .bootpg ADDR(.text) + 0x7f000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
+  } :text = 0xffff
 
   .resetvec ADDR(.text) + 0x7fffc :
   {
     *(.resetvec)
-  } = 0xffff
+  } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
 
@@ -131,7 +137,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
-  }
+  } :bss
 
   . = ALIGN(4);
   _end = . ;
diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds
index 0e4f5a2..515d320 100644
--- a/board/freescale/mpc8560ads/u-boot.lds
+++ b/board/freescale/mpc8560ads/u-boot.lds
@@ -26,6 +26,12 @@
 OUTPUT_ARCH(powerpc)
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -57,7 +63,7 @@ SECTIONS
     *(.text)
     *(.fixup)
     *(.got1)
-   }
+   } :text
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
@@ -66,7 +72,7 @@ SECTIONS
     *(.rodata1)
     *(.rodata.str1.4)
     *(.eh_frame)
-  }
+  } :text
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
@@ -118,12 +124,12 @@ SECTIONS
   .bootpg ADDR(.text) + 0x7f000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
+  } :text = 0xffff
 
   .resetvec ADDR(.text) + 0x7fffc :
   {
     *(.resetvec)
-  } = 0xffff
+  } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
 
@@ -134,7 +140,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
-  }
+  } :bss
 
   . = ALIGN(4);
   _end = . ;
diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds
index 9d245e4..ad96410 100644
--- a/board/freescale/mpc8568mds/u-boot.lds
+++ b/board/freescale/mpc8568mds/u-boot.lds
@@ -23,6 +23,12 @@
 OUTPUT_ARCH(powerpc)
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
     *(.text)
     *(.fixup)
     *(.got1)
-   }
+   } :text
     _etext = .;
     PROVIDE (etext = .);
     .rodata    :
@@ -63,7 +69,7 @@ SECTIONS
     *(.rodata1)
     *(.rodata.str1.4)
     *(.eh_frame)
-  }
+  } :text
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
@@ -115,12 +121,12 @@ SECTIONS
   .bootpg ADDR(.text) + 0x7f000 :
   {
     cpu/mpc85xx/start.o	(.bootpg)
-  } = 0xffff
+  } :text = 0xffff
 
   .resetvec ADDR(.text) + 0x7fffc :
   {
     *(.resetvec)
-  } = 0xffff
+  } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
 
@@ -131,7 +137,7 @@ SECTIONS
    *(.dynbss)
    *(.bss)
    *(COMMON)
-  }
+  } :bss
 
   . = ALIGN(4);
   _end = . ;
diff --git a/board/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
index a12f391..a12f391 100644
--- a/board/mx31ads/Makefile
+++ b/board/freescale/mx31ads/Makefile
diff --git a/board/mx31ads/config.mk b/board/freescale/mx31ads/config.mk
index d34dc02..d34dc02 100644
--- a/board/mx31ads/config.mk
+++ b/board/freescale/mx31ads/config.mk
diff --git a/board/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
index e166058..e166058 100644
--- a/board/mx31ads/lowlevel_init.S
+++ b/board/freescale/mx31ads/lowlevel_init.S
diff --git a/board/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
index dd0e150..c24c47c 100644
--- a/board/mx31ads/mx31ads.c
+++ b/board/freescale/mx31ads/mx31ads.c
@@ -55,16 +55,16 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* SPI2 */
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
 
 	/* start SPI2 clock */
 	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
diff --git a/board/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 49713d4..c379460 100644
--- a/board/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -37,11 +37,11 @@ SECTIONS
 	  /* WARNING - the following is hand-optimized to fit within	*/
 	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
-	  cpu/arm1136/start.o		(.text)
-	  board/mx31ads/libmx31ads.a	(.text)
-	  lib_arm/libarm.a		(.text)
-	  net/libnet.a			(.text)
-	  drivers/mtd/libmtd.a		(.text)
+	  cpu/arm1136/start.o			(.text)
+	  board/freescale/mx31ads/libmx31ads.a	(.text)
+	  lib_arm/libarm.a			(.text)
+	  net/libnet.a				(.text)
+	  drivers/mtd/libmtd.a			(.text)
 
 	  . = DEFINED(env_offset) ? env_offset : .;
 	  common/environment.o(.text)
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
index 15e86d3..2d4026a 100644
--- a/board/icecube/flash.c
+++ b/board/icecube/flash.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-#ifndef CFG_FLASH_CFI_DRIVER
+#ifndef CONFIG_FLASH_CFI_DRIVER
 flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
@@ -490,4 +490,4 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
 
 	return (res);
 }
-#endif /*CFG_FLASH_CFI_DRIVER*/
+#endif /*CONFIG_FLASH_CFI_DRIVER*/
diff --git a/board/imx31_litekit/imx31_litekit.c b/board/imx31_litekit/imx31_litekit.c
index 263dd9f..cb3e174 100644
--- a/board/imx31_litekit/imx31_litekit.c
+++ b/board/imx31_litekit/imx31_litekit.c
@@ -50,16 +50,16 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* SPI2 */
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
-	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
+	mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
 
 	/* start SPI2 clock */
 	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 42ecb1e..ae93444 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -54,11 +54,11 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* setup pins for I2C2 (for EEPROM, RTC) */
 	mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
-	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
+	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
 
 	gd->bd->bi_arch_number = 447;		/* board id for linux */
 	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 51874ea..0d90fb3 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -33,7 +33,7 @@
 #include <asm/bitops.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/ppc4xx-intvec.h>
+#include <asm/ppc4xx-uic.h>
 #include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -575,7 +575,7 @@ int checkboard(void)
  */
 void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
 }
 #endif
 
diff --git a/board/nc650/nand.c b/board/nc650/nand.c
index 8617f74..7dca97f 100644
--- a/board/nc650/nand.c
+++ b/board/nc650/nand.c
@@ -22,7 +22,7 @@
  */
 
 #include <common.h>
-
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NAND)
 
@@ -32,57 +32,49 @@
 /*
  *	hardware specific access to control-lines
  */
-static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
+static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
 
-	switch(cmd) {
-	case NAND_CTL_SETCLE:
-		this->IO_ADDR_W += 2;
-		break;
-	case NAND_CTL_CLRCLE:
-		this->IO_ADDR_W -= 2;
-		break;
-	case NAND_CTL_SETALE:
-		this->IO_ADDR_W += 1;
-		break;
-	case NAND_CTL_CLRALE:
-		this->IO_ADDR_W -= 1;
-		break;
-	case NAND_CTL_SETNCE:
-	case NAND_CTL_CLRNCE:
-		/* nop */
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			this->IO_ADDR_W += 2;
+		else
+			this->IO_ADDR_W -= 2;
+		if ( ctrl & NAND_ALE )
+			this->IO_ADDR_W += 1;
+		else
+			this->IO_ADDR_W -= 1;
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 #elif defined(CONFIG_IDS852_REV2)
 /*
  *	hardware specific access to control-lines
  */
-static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
+static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
 
-	switch(cmd) {
-	case NAND_CTL_SETCLE:
-		*(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0;
-		break;
-	case NAND_CTL_CLRCLE:
-		*(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
-		break;
-	case NAND_CTL_SETALE:
-		*(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0;
-		break;
-	case NAND_CTL_CLRALE:
-		*(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
-		break;
-	case NAND_CTL_SETNCE:
-		*(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
-		break;
-	case NAND_CTL_CLRNCE:
-		*(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0;
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			writeb(0, (volatile __u8 *) this->IO_ADDR_W + 0xa);
+		else
+			writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
+		if ( ctrl & NAND_ALE )
+			writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x9);
+		else
+			writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
+		if ( ctrl & NAND_NCE )
+			writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
+		else
+			writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0xc);
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 #else
 #error Unknown IDS852 module revision
@@ -93,11 +85,11 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
  * argument are board-specific (per include/linux/mtd/nand.h):
  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - eccm.ode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -109,8 +101,8 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
 int board_nand_init(struct nand_chip *nand)
 {
 
-	nand->hwcontrol = nc650_hwcontrol;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nc650_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->chip_delay = 12;
 /*	nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
 	return 0;
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
index b76d2a3..e3ab66f 100644
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -21,6 +21,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NAND)
 
@@ -32,24 +33,29 @@
 #define	MASK_CLE	0x02
 #define	MASK_ALE	0x04
 
-static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
 	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
 	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-	switch (cmd) {
-		case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break;
-		case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			IO_ADDR_W |= MASK_CLE;
+		if ( ctrl & NAND_ALE )
+			IO_ADDR_W |= MASK_ALE;
 	}
-	this->IO_ADDR_W = (void *) IO_ADDR_W;
+	this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
-	nand->eccmode = NAND_ECC_SOFT;
-	nand->hwcontrol = netstar_nand_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = netstar_nand_hwcontrol;
 	nand->chip_delay = 400;
 	return 0;
 }
diff --git a/board/netta/netta.c b/board/netta/netta.c
index 1183f33..bc31386 100644
--- a/board/netta/netta.c
+++ b/board/netta/netta.c
@@ -555,7 +555,7 @@ int board_early_init_f(void)
 	return 0;
 }
 
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 
 #include <linux/mtd/nand_legacy.h>
 
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index 131a62d..cc491d0 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -48,36 +48,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic0pr, 0xfffffe03);	/* per manual */
-	mtdcr (uic0tr, 0x01c00000);	/* per manual */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic1pr, 0xfffffe03);	/* per manual */
+	mtdcr (uic1tr, 0x01c00000);	/* per manual */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000); /* clear all */
-	mtdcr (uicb0er, 0x00000000); /* disable all */
-	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000); /* */
-	mtdcr (uicb0tr, 0x00000000); /* */
-	mtdcr (uicb0vr, 0x00000001); /* */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000); /* clear all */
+	mtdcr (uic0er, 0x00000000); /* disable all */
+	mtdcr (uic0cr, 0x00000000); /* all non-critical */
+	mtdcr (uic0pr, 0xfc000000); /* */
+	mtdcr (uic0tr, 0x00000000); /* */
+	mtdcr (uic0vr, 0x00000001); /* */
 
 	/* Setup shutdown/SSD empty interrupt as inputs */
 	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 097e183..99f5737 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -56,43 +56,24 @@ static struct alpr_ndfc_regs *alpr_ndfc = NULL;
  *
  * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
  */
-static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		hwctl |= 0x1;
-		break;
-	case NAND_CTL_CLRCLE:
-		hwctl &= ~0x1;
-		break;
-	case NAND_CTL_SETALE:
-		hwctl |= 0x2;
-		break;
-	case NAND_CTL_CLRALE:
-		hwctl &= ~0x2;
-		break;
-	case NAND_CTL_SETNCE:
-		break;
-	case NAND_CTL_CLRNCE:
-		writeb(0x00, &(alpr_ndfc->term));
-		break;
-	}
-}
-
-static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
-	struct nand_chip *nand = mtd->priv;
+	struct nand_chip *this = mtd->priv;
 
-	if (hwctl & 0x1)
-		/*
-		 * IO_ADDR_W used as CMD[i] reg to support multiple NAND
-		 * chips.
-		 */
-		writeb(byte, nand->IO_ADDR_W);
-	else if (hwctl & 0x2) {
-		writeb(byte, &(alpr_ndfc->addr_wait));
-	} else
-		writeb(byte, &(alpr_ndfc->data));
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			hwctl |= 0x1;
+		else
+			hwctl &= ~0x1;
+		if ( ctrl & NAND_ALE )
+			hwctl |= 0x2;
+		else
+			hwctl &= ~0x2;
+		if ( (ctrl & NAND_NCE) != NAND_NCE)
+			writeb(0x00, &(alpr_ndfc->term));
+	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static u_char alpr_nand_read_byte(struct mtd_info *mtd)
@@ -158,12 +139,10 @@ int board_nand_init(struct nand_chip *nand)
 {
 	alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
 
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 
 	/* Reference hardware control function */
-	nand->hwcontrol  = alpr_nand_hwcontrol;
-	/* Set command delay time */
-	nand->write_byte = alpr_nand_write_byte;
+	nand->cmd_ctrl  = alpr_nand_hwcontrol;
 	nand->read_byte  = alpr_nand_read_byte;
 	nand->write_buf  = alpr_nand_write_buf;
 	nand->read_buf   = alpr_nand_read_buf;
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
index 518ea9c..0786324 100644
--- a/board/prodrive/pdnb3/flash.c
+++ b/board/prodrive/pdnb3/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
-#if !defined(CFG_FLASH_CFI_DRIVER)
+#if !defined(CONFIG_FLASH_CFI_DRIVER)
 
 /*
  * include common flash code (for esd boards)
@@ -86,4 +86,4 @@ unsigned long flash_init(void)
 	return size;
 }
 
-#endif /* CFG_FLASH_CFI_DRIVER */
+#endif /* CONFIG_FLASH_CFI_DRIVER */
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
index b1e7041..1ce3c8c 100644
--- a/board/prodrive/pdnb3/nand.c
+++ b/board/prodrive/pdnb3/nand.c
@@ -52,40 +52,26 @@ static struct pdnb3_ndfc_regs *pdnb3_ndfc;
  *
  * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
  */
-static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		hwctl |= 0x1;
-		break;
-	case NAND_CTL_CLRCLE:
-		hwctl &= ~0x1;
-		break;
-
-	case NAND_CTL_SETALE:
-		hwctl |= 0x2;
-		break;
-	case NAND_CTL_CLRALE:
-		hwctl &= ~0x2;
-		break;
-
-	case NAND_CTL_SETNCE:
-		break;
-	case NAND_CTL_CLRNCE:
-		writeb(0x00, &(pdnb3_ndfc->term));
-		break;
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			hwctl |= 0x1;
+		else
+			hwctl &= ~0x1;
+		if ( ctrl & NAND_ALE )
+			hwctl |= 0x2;
+		else
+			hwctl &= ~0x2;
+		if ( (ctrl & NAND_NCE) != NAND_NCE)
+			writeb(0x00, &(pdnb3_ndfc->term));
 	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
-static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
-	if (hwctl & 0x1)
-		writeb(byte, &(pdnb3_ndfc->cmd));
-	else if (hwctl & 0x2)
-		writeb(byte, &(pdnb3_ndfc->addr));
-	else
-		writeb(byte, &(pdnb3_ndfc->data));
-}
 
 static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
 {
@@ -152,16 +138,13 @@ int board_nand_init(struct nand_chip *nand)
 {
 	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
 
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 
 	/* Set address of NAND IO lines (Using Linear Data Access Region) */
 	nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
 	nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
 	/* Reference hardware control function */
-	nand->hwcontrol  = pdnb3_nand_hwcontrol;
-	/* Set command delay time */
-	nand->hwcontrol  = pdnb3_nand_hwcontrol;
-	nand->write_byte = pdnb3_nand_write_byte;
+	nand->cmd_ctrl   = pdnb3_nand_hwcontrol;
 	nand->read_byte  = pdnb3_nand_read_byte;
 	nand->write_buf  = pdnb3_nand_write_buf;
 	nand->read_buf   = pdnb3_nand_read_buf;
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index 2d71d3b..72ce976 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -195,36 +195,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------+
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 +-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000000);	/* all non- critical */
-	mtdcr (uic0pr, 0xfffffe03);	/* polarity */
-	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */
-	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (uic1cr, 0x00000000);	/* all non- critical */
+	mtdcr (uic1pr, 0xfffffe03);	/* polarity */
+	mtdcr (uic1tr, 0x01c00000);	/* trigger edge vs level */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffff83ff);	/* polarity */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic2pr, 0xffffc8ff);	/* polarity */
+	mtdcr (uic2tr, 0x00ff0000);	/* trigger edge vs level */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
-	mtdcr (uicb0er, 0x00000000);	/* disable all */
-	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000);
-	mtdcr (uicb0tr, 0x00000000);
-	mtdcr (uicb0vr, 0x00000001);
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffff83ff);	/* polarity */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic0pr, 0xfc000000);
+	mtdcr (uic0tr, 0x00000000);
+	mtdcr (uic0vr, 0x00000001);
 
 	fpga_init();
 
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 66cdfb1..c38850d 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -185,36 +185,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------+
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 +-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000000);	/* all non- critical */
-	mtdcr (uic0pr, 0xfffffe03);	/* polarity */
-	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */
-	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (uic1cr, 0x00000000);	/* all non- critical */
+	mtdcr (uic1pr, 0xfffffe03);	/* polarity */
+	mtdcr (uic1tr, 0x01c00000);	/* trigger edge vs level */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffff83ff);	/* polarity */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic2pr, 0xffffc8ff);	/* polarity */
+	mtdcr (uic2tr, 0x00ff0000);	/* trigger edge vs level */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
-	mtdcr (uicb0er, 0x00000000);	/* disable all */
-	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000);
-	mtdcr (uicb0tr, 0x00000000);
-	mtdcr (uicb0vr, 0x00000001);
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffff83ff);	/* polarity */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic0pr, 0xfc000000);
+	mtdcr (uic0tr, 0x00000000);
+	mtdcr (uic0vr, 0x00000001);
 
 	fpga_init();
 
diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c
index 009567b..45eff28 100644
--- a/board/sc3/sc3nand.c
+++ b/board/sc3/sc3nand.c
@@ -39,30 +39,26 @@
 static void *sc3_io_base;
 static void *sc3_control_base = (void *)0xEF600700;
 
-static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		set_bit (SC3_NAND_CLE, sc3_control_base);
-		break;
-	case NAND_CTL_CLRCLE:
-		clear_bit (SC3_NAND_CLE, sc3_control_base);
-		break;
-
-	case NAND_CTL_SETALE:
-		set_bit (SC3_NAND_ALE, sc3_control_base);
-		break;
-	case NAND_CTL_CLRALE:
-		clear_bit (SC3_NAND_ALE, sc3_control_base);
-		break;
-
-	case NAND_CTL_SETNCE:
-		set_bit (SC3_NAND_CE, sc3_control_base);
-		break;
-	case NAND_CTL_CLRNCE:
-		clear_bit (SC3_NAND_CE, sc3_control_base);
-		break;
+	struct nand_chip *this = mtd->priv;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			set_bit (SC3_NAND_CLE, sc3_control_base);
+		else
+			clear_bit (SC3_NAND_CLE, sc3_control_base);
+		if ( ctrl & NAND_ALE )
+			set_bit (SC3_NAND_ALE, sc3_control_base);
+		else
+			clear_bit (SC3_NAND_ALE, sc3_control_base);
+		if ( ctrl & NAND_NCE )
+			set_bit (SC3_NAND_CE, sc3_control_base);
+		else
+			clear_bit (SC3_NAND_CE, sc3_control_base);
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static int sc3_nand_dev_ready(struct mtd_info *mtd)
@@ -79,14 +75,14 @@ static void sc3_select_chip(struct mtd_info *mtd, int chip)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 
 	sc3_io_base = (void *) CFG_NAND_BASE;
 	/* Set address of NAND IO lines (Using Linear Data Access Region) */
 	nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
 	nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
 	/* Reference hardware control function */
-	nand->hwcontrol  = sc3_nand_hwcontrol;
+	nand->cmd_ctrl  = sc3_nand_hwcontrol;
 	nand->dev_ready  = sc3_nand_dev_ready;
 	nand->select_chip = sc3_select_chip;
 	return 0;
diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index cde0296..a0ec254 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -1068,24 +1068,22 @@ int update_flash_size (int flash_size)
 
 static u8 hwctl = 0;
 
-static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		hwctl |= 0x1;
-		break;
-	case NAND_CTL_CLRCLE:
-		hwctl &= ~0x1;
-		break;
-
-	case NAND_CTL_SETALE:
-		hwctl |= 0x2;
-		break;
-
-	case NAND_CTL_CLRALE:
-		hwctl &= ~0x2;
-		break;
+	struct nand_chip *this = mtd->priv;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			hwctl |= 0x1;
+		else
+			hwctl &= ~0x1;
+		if ( ctrl & NAND_ALE )
+			hwctl |= 0x2;
+		else
+			hwctl &= ~0x2;
 	}
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
@@ -1188,9 +1186,9 @@ int board_nand_init(struct nand_chip *nand)
 	memctl->memc_br3 = CFG_NAND_BR;
 	memctl->memc_mbmr = (MxMR_OP_NORM);
 
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 
-	nand->hwcontrol	 = upmnand_hwcontrol;
+	nand->cmd_ctrl	 = upmnand_hwcontrol;
 	nand->read_byte	 = upmnand_read_byte;
 	nand->write_byte = upmnand_write_byte;
 	nand->dev_ready	 = tqm8272_dev_ready;
diff --git a/board/tqc/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c
index 4342ebc..1231c7c 100644
--- a/board/tqc/tqm8xx/flash.c
+++ b/board/tqc/tqm8xx/flash.c
@@ -33,7 +33,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
+#if !defined(CONFIG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
 
 #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
     && !defined(CONFIG_TQM885D)
@@ -831,4 +831,4 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
 /*-----------------------------------------------------------------------
  */
 
-#endif /* !defined(CFG_FLASH_CFI_DRIVER) */
+#endif /* !defined(CONFIG_FLASH_CFI_DRIVER) */
diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile
new file mode 100644
index 0000000..7283704
--- /dev/null
+++ b/board/xilinx/ml507/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+endif
+
+INCS		:=
+CFLAGS		+= $(INCS)
+HOST_CFLAGS	+= $(INCS)
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xilinx/ml507/config.mk b/board/xilinx/ml507/config.mk
new file mode 100644
index 0000000..e827e8a
--- /dev/null
+++ b/board/xilinx/ml507/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0x04000000
+endif
diff --git a/board/xilinx/ml507/init.S b/board/xilinx/ml507/init.S
new file mode 100644
index 0000000..3228a65
--- /dev/null
+++ b/board/xilinx/ml507/init.S
@@ -0,0 +1,53 @@
+/*
+ *  (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+.section .bootpg,"ax"
+.globl tlbtab
+
+tlbtab:
+tlbtab_start
+	/* SDRAM */
+tlbentry(XPAR_DDR2_SDRAM_MEM_BASEADDR, SZ_256M, CFG_SDRAM_BASE, 0,
+	 AC_R | AC_W | AC_X | SA_G | SA_I)
+	/* UART */
+tlbentry(XPAR_UARTLITE_0_BASEADDR, SZ_64K, XPAR_UARTLITE_0_BASEADDR, 0,
+	 AC_R | AC_W | SA_G | SA_I)
+	/* PIC */
+tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0,
+	 AC_R | AC_W | SA_G | SA_I)
+#ifdef XPAR_IIC_EEPROM_BASEADDR
+	/* I2C */
+tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0,
+	 AC_R | AC_W | SA_G | SA_I)
+#endif
+#ifdef XPAR_LLTEMAC_0_BASEADDR
+	/* Net */
+tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0,
+	 AC_R | AC_W | SA_G | SA_I)
+#endif
+#ifdef XPAR_FLASH_MEM0_BASEADDR
+	/*Flash*/
+tlbentry(XPAR_FLASH_MEM0_BASEADDR, SZ_256M, XPAR_FLASH_MEM0_BASEADDR, 0,
+	 AC_R | AC_W | AC_X | SA_G | SA_I)
+#endif
+tlbtab_end
diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c
new file mode 100644
index 0000000..d499303
--- /dev/null
+++ b/board/xilinx/ml507/ml507.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+int board_pre_init(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("ML507 Board\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+			    CFG_SDRAM_SIZE_MB * 1024 * 1024);
+}
+
+void get_sys_info(sys_info_t * sysInfo)
+{
+	sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+	sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+	sysInfo->freqPCI = 0;
+
+	return;
+}
diff --git a/board/xilinx/ml507/u-boot-ram.lds b/board/xilinx/ml507/u-boot-ram.lds
new file mode 100644
index 0000000..2c98d27
--- /dev/null
+++ b/board/xilinx/ml507/u-boot-ram.lds
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start_440)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xilinx/ml507/u-boot-rom.lds b/board/xilinx/ml507/u-boot-rom.lds
new file mode 100644
index 0000000..d5da018
--- /dev/null
+++ b/board/xilinx/ml507/u-boot-rom.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start_440)
+
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h
new file mode 100644
index 0000000..77d2ddf
--- /dev/null
+++ b/board/xilinx/ml507/xparameters.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 	0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR 	0x81600000
+#define XPAR_INTC_0_BASEADDR 		0x81800000
+#define XPAR_LLTEMAC_0_BASEADDR 	0x81C00000
+#define XPAR_UARTLITE_0_BASEADDR 	0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 	0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 	400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 	13
+#define XPAR_UARTLITE_0_BAUDRATE	9600
+
+#endif
diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
index bc7e3bd..c94a345 100644
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -59,36 +59,48 @@ int board_early_init_f(void)
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000003);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic0pr, 0xfffffe00);	/* per ref-board manual */
-	mtdcr (uic0tr, 0x01c00000);	/* per ref-board manual */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffc0ff);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x00ff8000);	/* per ref-board manual */
+	mtdcr (uic1cr, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic1pr, 0xfffffe00);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x01c00000);	/* per ref-board manual */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2pr, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8000);	/* per ref-board manual */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000); /* clear all */
-	mtdcr (uicb0er, 0x00000000); /* disable all */
-	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000); /* */
-	mtdcr (uicb0tr, 0x00000000); /* */
-	mtdcr (uicb0vr, 0x00000001); /* */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000); /* clear all */
+	mtdcr (uic0er, 0x00000000); /* disable all */
+	mtdcr (uic0cr, 0x00000000); /* all non-critical */
+	mtdcr (uic0pr, 0xfc000000); /* */
+	mtdcr (uic0tr, 0x00000000); /* */
+	mtdcr (uic0vr, 0x00000001); /* */
 
 	LED0_ON();
 
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index ca16578..09bcbb2 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -69,7 +69,7 @@ static struct nand_oobinfo delta_oob = {
 /*
  * not required for Monahans DFC
  */
-static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	return;
 }
@@ -110,25 +110,6 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 }
 
 
-/*
- * These functions are quite problematic for the DFC. Luckily they are
- * not used in the current nand code, except for nand_command, which
- * we've defined our own anyway. The problem is, that we always need
- * to write 4 bytes to the DFC Data Buffer, but in these functions we
- * don't know if to buffer the bytes/half words until we've gathered 4
- * bytes or if to send them straight away.
- *
- * Solution: Don't use these with Mona's DFC and complain loudly.
- */
-static void dfc_write_word(struct mtd_info *mtd, u16 word)
-{
-	printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
-}
-static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
-{
-	printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
-}
-
 /* The original:
  * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
  *
@@ -168,7 +149,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
  */
 static u16 dfc_read_word(struct mtd_info *mtd)
 {
-	printf("dfc_write_byte: UNIMPLEMENTED.\n");
+	printf("dfc_read_word: UNIMPLEMENTED.\n");
 	return 0;
 }
 
@@ -289,9 +270,10 @@ static void dfc_new_cmd(void)
 
 /* this function is called after Programm and Erase Operations to
  * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
 {
 	unsigned long ndsr=0, event=0;
+	int state = this->state;
 
 	if(state == FL_WRITING) {
 		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
@@ -435,11 +417,11 @@ static void dfc_gpio_init(void)
  * argument are board-specific (per include/linux/mtd/nand_new.h):
  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -560,21 +542,18 @@ int board_nand_init(struct nand_chip *nand)
 	/* wait 10 us due to cmd buffer clear reset */
 	/*	wait(10); */
 
-
-	nand->hwcontrol = dfc_hwcontrol;
+	nand->cmd_ctrl = dfc_hwcontrol;
 /*	nand->dev_ready = dfc_device_ready; */
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->options = NAND_BUSWIDTH_16;
 	nand->waitfunc = dfc_wait;
 	nand->read_byte = dfc_read_byte;
-	nand->write_byte = dfc_write_byte;
 	nand->read_word = dfc_read_word;
-	nand->write_word = dfc_write_word;
 	nand->read_buf = dfc_read_buf;
 	nand->write_buf = dfc_write_buf;
 
 	nand->cmdfunc = dfc_cmdfunc;
-	nand->autooob = &delta_oob;
+/*	nand->autooob = &delta_oob; */
 	nand->badblock_pattern = &delta_bbt_descr;
 	return 0;
 }