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authorAnatolij Gustschin <agust@denx.de>2013-02-08 00:03:49 +0000
committerWolfgang Denk <wd@denx.de>2013-03-09 08:23:02 +0100
commita615dfda8c2041dd98ecd238d45f3bc35e495b44 (patch)
treeb177e8e05649ba7da7f8f7dcfe309fb29b7aef68 /board
parentfcc7fe425183f9ec95fba33d041eb359d0a3a598 (diff)
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mpc512x: Adjust the DRAM init sequence to the datasheet spec
Do maintain a 200 usecs period of stable power and clock before asserting the CKE signal and sending commands, have at least 200 DRAM clock cycles pass after initialization before data access. Signed-off-by: Anatolij Gustschin <agust@denx.de>
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