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authorStefan Roese <sr@denx.de>2005-11-08 09:00:09 +0100
committerStefan Roese <sr@denx.de>2005-11-08 09:00:09 +0100
commitea339205a94706d8b9170bbd89e8c1373df9a92f (patch)
treed5108ecddb9c5ffa9e1e4bb53b1a4a1437712920 /board
parent527b5a511c804074eebfc08c9ae7860b6717da85 (diff)
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Updated PCI mapping for esd CPCI2DP board.
Add support for error LED. Patch by Matthias Fuchs, 07 Nov 2005
Diffstat (limited to 'board')
-rw-r--r--board/esd/cpci2dp/cpci2dp.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index 727640e..b463f0e 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -31,14 +31,17 @@ int board_early_init_f (void)
unsigned long cntrl0Reg;
/*
- * Setup GPIO pins (CS4 as GPIO)
+ * Setup GPIO pins (CS4+CS7 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00800000);
-
- out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* set output pins to high */
- out32(GPIO0_ODR, CFG_INTA_FAKE); /* INTA# is open drain */
- out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP); /* setup for output */
+ mtdcr(cntrl0, cntrl0Reg | 0x00900000);
+
+ /* set output pins to high */
+ out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
+ /* INTA# is open drain */
+ out32(GPIO0_ODR, CFG_INTA_FAKE);
+ /* setup for output */
+ out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive