MLK-12436-2: mx6qarm2: update ddr scripts

ALign with imx_v2015.04.
Also to lpddr2 support:
From commit: "620cf5f3d4cf37b065b5857a8ea91d61bf6c471d"
"
Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board,
but there is a problem in switching pre_periph_clk_sel to pll2_pfd2.
We cannot directly change the parent of pre_periph_clk_sel as this mux
is not a glitchless mux. We need to follow the correct procedure and wait
for the busy bits to clear before switching.
Change to follow the procedure:
1. Set periph_clk2 to OSC.
2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for
periph_clk , ahb_podf and axi_podf busy bits.
3. Setting the pre_periph_clk to PLL2 PFD 396M.
4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR
busy bits.
"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
(cherry picked from commit febf98c68853030ce5c1f9124e77d75456e71314)

1 files changed, 176 insertions, 1 deletions

diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index 5c6a202..957156f 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -27,6 +27,10 @@ BOOT_FROM	sd
 PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000
 #else
 
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
 /*
  * Device Configuration Data (DCD)
  *
@@ -38,8 +42,179 @@ PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000
  *	Address	  absolute address of the register
  *	value	  value to be stored in the register
  */
-#ifdef CONFIG_MX6DQ_LPDDR2
+#ifdef CONFIG_MX6DQ_POP_LPDDR2
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* DCD */
+DATA 4 0x020e0798 0x00080000
+DATA 4 0x020e0758 0x00000000
+
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00003030
+DATA 4 0x020e05b0 0x00003030
+DATA 4 0x020e0524 0x00003030
+DATA 4 0x020e051c 0x00003030
+DATA 4 0x020e0518 0x00003030
+DATA 4 0x020e050c 0x00003030
+DATA 4 0x020e05b8 0x00003030
+DATA 4 0x020e05c0 0x00003030
+
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b401c 0x00008000
+
+DATA 4 0x021b085c 0x1B5F0107
+DATA 4 0x021b485c 0x1B5F0107
+
+DATA 4 0x021b0800 0xA1390003
+
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b4890 0x00400000
+
+DATA 4 0x021b0848 0x3C3A3A44
+DATA 4 0x021b4848 0x3C3A3A44
+
+DATA 4 0x021b0850 0x4238423A
+DATA 4 0x021b4850 0x4238423A
+
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x00000000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b482c 0xf3333333
+DATA 4 0x021b4830 0xf3333333
+DATA 4 0x021b4834 0xf3333333
+DATA 4 0x021b4838 0xf3333333
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b000c 0x444961A5
+DATA 4 0x021b0010 0x00160E83
+DATA 4 0x021b0014 0x000000DD
+
+DATA 4 0x021b0018 0x0000174C
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x149F26D2
+DATA 4 0x021b0030 0x00000010
+DATA 4 0x021b0038 0x0021099B
+DATA 4 0x021b0040 0x0000004F
+DATA 4 0x021b0400 0x11420000
+DATA 4 0x021b0000 0x83110000
+
+DATA 4 0x021b4004 0x00020036
+DATA 4 0x021b4008 0x00000000
+DATA 4 0x021b400c 0x444961A5
+DATA 4 0x021b4010 0x00160E83
+DATA 4 0x021b4014 0x000000DD
+
+DATA 4 0x021b4018 0x0000174C
+DATA 4 0x021b401c 0x00008000
+DATA 4 0x021b402c 0x149F26D2
+DATA 4 0x021b4030 0x00000010
+DATA 4 0x021b4038 0x0021099B
+DATA 4 0x021b4040 0x00000017
+DATA 4 0x021b4400 0x11420000
+DATA 4 0x021b4000 0x83110000
+
+DATA 4 0x021b001c 0x003F8030
+DATA 4 0x021b001c 0xFF0A8030
+DATA 4 0x021b001c 0xC2018030
+DATA 4 0x021b001c 0x06028030
+DATA 4 0x021b001c 0x02038030
+
+DATA 4 0x021b401c 0x003F8030
+DATA 4 0x021b401c 0xFF0A8030
+DATA 4 0x021b401c 0xC2018030
+DATA 4 0x021b401c 0x06028030
+DATA 4 0x021b401c 0x02038030
+
+DATA 4 0x021b0800 0xA1390003
+
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b4020 0x00001800
+
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b4818 0x00000000
+
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b4004 0x00025576
+
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b4404 0x00011006
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b401c 0x00000000
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+
+#elif defined(CONFIG_MX6DQ_LPDDR2)
 /* DCD */
+DATA 4 0x020C4018 0x21324
+DATA 4 0x020C4014 0x2018D00
+CHECK_BITS_CLR 4 0x020C4048 0x3F
+DATA 4 0x020C4018 0x61324
+DATA 4 0x020C4014 0x18D00
+CHECK_BITS_CLR 4 0x020C4048 0x3F
 DATA 4 0x020C4018 0x60324
 
 DATA 4 0x020E05a8 0x00003038