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authorTom Rini <trini@konsulko.com>2015-08-31 12:12:27 -0400
committerTom Rini <trini@konsulko.com>2015-08-31 12:12:27 -0400
commitb7e84c93c450480ca4ff51ad2eb56bd83c1dc368 (patch)
tree1523b49f2bd4d1880bfa12f22e11cb6ef66d2e3b /board
parent80cd58b99e8690b05e8537dbf76276e24fcfa652 (diff)
parentfa5e102019e28a5936e52d6aa9f5624cf1744a35 (diff)
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Merge branch 'master' of http://git.denx.de/u-boot-sunxi
Diffstat (limited to 'board')
-rw-r--r--board/sunxi/Kconfig1
-rw-r--r--board/sunxi/MAINTAINERS10
-rw-r--r--board/sunxi/board.c34
3 files changed, 34 insertions, 11 deletions
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index fd6668f..55906b5 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -425,6 +425,7 @@ config VIDEO_LCD_MODE
LCD panel timing details string, leave empty if there is no LCD panel.
This is in drivers/video/videomodes.c: video_get_params() format, e.g.
x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
+ Also see: http://linux-sunxi.org/LCD
config VIDEO_LCD_DCLK_PHASE
int "LCD panel display clock phase"
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 1b44ce8..3a4d1fb 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -8,9 +8,9 @@ F: configs/ba10_tv_box_defconfig
F: configs/Chuwi_V7_CW0825_defconfig
F: configs/Cubieboard_defconfig
F: configs/Hyundai_A7HD_defconfig
+F: configs/inet97fv2_defconfig
F: configs/jesurun_q5_defconfig
F: configs/Mele_A1000_defconfig
-F: configs/Mele_A1000G_quad_defconfig
F: configs/Mele_M3_defconfig
F: configs/Mini-X_defconfig
F: configs/mk802_defconfig
@@ -21,11 +21,13 @@ F: configs/A13-OLinuXino_defconfig
F: configs/A13-OLinuXinoM_defconfig
F: configs/Auxtek-T003_defconfig
F: configs/Auxtek-T004_defconfig
+F: configs/inet98v_rev2_defconfig
F: configs/mk802_a10s_defconfig
F: configs/r7-tv-dongle_defconfig
F: configs/UTOO_P66_defconfig
F: include/configs/sun6i.h
F: configs/CSQ_CS908_defconfig
+F: configs/Mele_A1000G_quad_defconfig
F: configs/Mele_M9_defconfig
F: include/configs/sun7i.h
F: configs/A20-OLinuXino_MICRO_defconfig
@@ -40,11 +42,17 @@ F: configs/qt840a_defconfig
F: configs/Wits_Pro_A20_DKT_defconfig
F: include/configs/sun8i.h
F: configs/ga10h_v1_1_defconfig
+F: configs/gt90h_v4_defconfig
F: configs/Ippo_q8h_v1_2_defconfig
F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig
F: include/configs/sun9i.h
F: configs/Merrii_A80_Optimus_defconfig
+A20-OLIMEX-SOM-EVB BOARD
+M: Marcus Cooper <codekipper@gmail.com>
+S: Maintained
+F: configs/A20-Olimex-SOM-EVB_defconfig
+
A20-OLINUXINO-LIME BOARD
M: FUKAUMI Naoki <naobsd@gmail.com>
S: Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index f85e825..9c855f6 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -31,6 +31,7 @@
#include <asm/arch/usb_phy.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <nand.h>
#include <net.h>
#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
@@ -107,26 +108,44 @@ int dram_init(void)
return 0;
}
-#if defined(CONFIG_SPL_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
static void nand_pinmux_setup(void)
{
unsigned int pin;
- for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++)
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
- for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++)
+ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
+ for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
+#endif
+ /* sun4i / sun7i do have a PC23, but it is not used for nand,
+ * only sun7i has a PC24 */
+#ifdef CONFIG_MACH_SUN7I
sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
+#endif
}
static void nand_clock_setup(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
+#ifdef CONFIG_MACH_SUN9I
+ setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
+#else
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
+#endif
setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
}
+
+void board_nand_init(void)
+{
+ nand_pinmux_setup();
+ nand_clock_setup();
+}
#endif
#ifdef CONFIG_GENERIC_MMC
@@ -437,7 +456,7 @@ void sunxi_board_init(void)
#ifdef CONFIG_AXP221_POWER
power_failed = axp221_init();
power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT);
- power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */
+ power_failed |= axp221_set_dcdc2(CONFIG_AXP221_DCDC2_VOLT);
power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */
#ifdef CONFIG_MACH_SUN6I
power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */
@@ -453,11 +472,6 @@ void sunxi_board_init(void)
power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT);
#endif
-#ifdef CONFIG_SPL_NAND_SUNXI
- nand_pinmux_setup();
- nand_clock_setup();
-#endif
-
printf("DRAM:");
ramsize = sunxi_dram_init();
printf(" %lu MiB\n", ramsize >> 20);