Add initial support iMX6Q for igep0046 defconfig

Add RAM support iMX6Q
Updated default .dtb file defconfig
eeprom clean up
I2C SCL low bus lock fix
Add Audio Reset
Changed I2C MUX - no pullups

Signed-off-by: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>

3 files changed, 176 insertions, 22 deletions

diff --git a/board/isee/igep0046/igep0046.c b/board/isee/igep0046/igep0046.c
index f02c541..ce11717 100644
--- a/board/isee/igep0046/igep0046.c
+++ b/board/isee/igep0046/igep0046.c
@@ -64,9 +64,8 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 #ifdef CONFIG_SYS_I2C
-#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |	\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE 	  | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL  ( PAD_CTL_ODE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 #define I2C_PMIC	1
 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
 #endif
@@ -166,11 +165,14 @@ static iomux_v3_cfg_t const init_pads[] =
 	MX6_PAD_DI0_PIN4__GPIO4_IO20  | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
 	MX6_PAD_DI0_PIN15__GPIO4_IO17 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
 	#ifdef CONFIG_BASE0040
-	/* GPIO USB BASE0040 MUX */
-	MX6_PAD_CSI0_DAT4__GPIO5_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_HUB_RESET
-	MX6_PAD_CSI0_DAT5__GPIO5_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_PWR1
-	MX6_PAD_CSI0_DAT6__GPIO5_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_PWR2
-	MX6_PAD_CSI0_DAT7__GPIO5_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB_PWR3
+	/* TLV320AIC3106 Audio codec Reset*/
+	MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* USB2514 HUB Reset */
+	MX6_PAD_CSI0_DAT4__GPIO5_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* USB Power Lines */
+	MX6_PAD_CSI0_DAT5__GPIO5_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_CSI0_DAT6__GPIO5_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_CSI0_DAT7__GPIO5_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	#endif
 };
 
@@ -228,6 +230,13 @@ static iomux_v3_cfg_t const usb_otg_pads[] =
 };
 
 #ifdef CONFIG_BASE0040
+static void reset_audio(void)
+{
+	/* Audio Reset */
+	gpio_direction_output(IMX_GPIO_NR(4, 10), 0);
+	mdelay(5);
+}
+
 static void reset_usb_hub(void)
 {
 	/* Activate USB_PWRx */
@@ -394,8 +403,6 @@ int board_early_init_f(void)
 	gpio_direction_output(IMX_GPIO_NR(4, 19), 1);
 	gpio_direction_output(IMX_GPIO_NR(4, 20), 0);
 	gpio_direction_output(IMX_GPIO_NR(4, 17), 1);
-
-
 	return 0;
 }
 
@@ -404,28 +411,33 @@ int board_init(void)
 	u32 crc_value = 0;
    	u32 crc_save_value = 0;
 
+#ifdef CONFIG_BASE0040
+	reset_audio();
+#endif
+
 #ifdef CONFIG_SYS_I2C
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	mdelay(1);
 #endif
 
-if(check_eeprom() != 0){
+    if(check_eeprom() != 0){
 	printf("EEPROM: not found\n");
-}else{
-	/* Read configuration from eeprom */
-	if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup)))
+    }else{
+		/* Read configuration from eeprom */
+		if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup)))
 	  	printf("EEPROM: read fail\n");	
-	/* Verify crc32 */
+		/* Verify crc32 */
 	   	crc_save_value = igep0046_eeprom_config.crc32;
     	igep0046_eeprom_config.crc32 = 0;
 	   	crc_value = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
-	if(crc_save_value != crc_value){
+		if(crc_save_value != crc_value){
        	printf("EEPROM: CRC32 failed. Loading default MAC\n");				
-	}else{
+		}else{
 	    printf("EEPROM: CRC32 OK! Loading MAC from eeprom\n");	       		
 	  	igep_eeprom_valid = 1;
+		}
 	}
-}
 
 #ifdef CONFIG_BASE0040
 	reset_usb_hub();
diff --git a/board/isee/igep0046/igep0046_eeprom.c b/board/isee/igep0046/igep0046_eeprom.c
index 9d3bc25..33bf1f3 100644
--- a/board/isee/igep0046/igep0046_eeprom.c
+++ b/board/isee/igep0046/igep0046_eeprom.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
  *
- * EEPROM support source file for igep0046
+ * EEPROM support source file for IGEP0046 board
  *
  * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
  *
@@ -51,10 +51,10 @@ int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
 
 int check_eeprom (void)
 {
-	i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-	/* Check if baseboard eeprom is available */
+    i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+    /* Check if baseboard eeprom is available */
 	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		debug("Could not probe the EEPROM at 0x%x\n",
+		printf("Could not probe the EEPROM at 0x%x\n",
 		       CONFIG_SYS_I2C_EEPROM_ADDR);
 		return -1;
 	}
diff --git a/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg b/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
new file mode 100644
index 0000000..dd10a58
--- /dev/null
+++ b/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
@@ -0,0 +1,142 @@
+/*

+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz

+ *

+ * SPDX-License-Identifier:	GPL-2.0+

+ *

+ * Refer docs/README.imxmage for more details about how-to configure

+ * and create imximage boot image

+ *

+ * The syntax is taken as close as possible with the kwbimage

+ */

+

+/* image version */

+

+IMAGE_VERSION 2

+

+/*

+ * Boot Device : one of

+ * spi, sd (the board has no nand neither onenand)

+ */

+

+BOOT_FROM	sd

+

+/*

+ * Device Configuration Data (DCD)

+ *

+ * Each entry must have the format:

+ * Addr-type           Address        Value

+ *

+ * where:

+ *	Addr-type register length (1,2 or 4 bytes)

+ *	Address	  absolute address of the register

+ *	value	  value to be stored in the register

+ */

+DATA 4, 0x020e0798, 0x000C0000

+DATA 4, 0x020e0758, 0x00000000

+DATA 4, 0x020e0588, 0x00020030

+DATA 4, 0x020e0594, 0x00020030

+DATA 4, 0x020e056c, 0x00020030

+DATA 4, 0x020e0578, 0x00020030

+DATA 4, 0x020e074c, 0x00000030

+DATA 4, 0x020e057c, 0x00020030

+DATA 4, 0x020e058c, 0x00000000

+DATA 4, 0x020e059c, 0x00003030

+DATA 4, 0x020e05a0, 0x00003030

+DATA 4, 0x020e078c, 0x00000030

+DATA 4, 0x020e0750, 0x00020000

+DATA 4, 0x020e05a8, 0x00000030

+DATA 4, 0x020e05b0, 0x00000030

+DATA 4, 0x020e0524, 0x00000030

+DATA 4, 0x020e051c, 0x00000030

+DATA 4, 0x020e0518, 0x00000030

+DATA 4, 0x020e050c, 0x00000030

+DATA 4, 0x020e05b8, 0x00000030

+DATA 4, 0x020e05c0, 0x00000030

+DATA 4, 0x020e0774, 0x00020000

+DATA 4, 0x020e0784, 0x00000030

+DATA 4, 0x020e0788, 0x00000030

+DATA 4, 0x020e0794, 0x00000030

+DATA 4, 0x020e079c, 0x00000030

+DATA 4, 0x020e07a0, 0x00000030

+DATA 4, 0x020e07a4, 0x00000030

+DATA 4, 0x020e07a8, 0x00000030

+DATA 4, 0x020e0748, 0x00000030

+DATA 4, 0x020e05ac, 0x00020030

+DATA 4, 0x020e05b4, 0x00020030

+DATA 4, 0x020e0528, 0x00020030

+DATA 4, 0x020e0520, 0x00020030

+DATA 4, 0x020e0514, 0x00020030

+DATA 4, 0x020e0510, 0x00020030

+DATA 4, 0x020e05bc, 0x00020030

+DATA 4, 0x020e05c4, 0x00020030

+DATA 4, 0x021b0800, 0xa1390003

+DATA 4, 0x021b080c, 0x001F001F

+DATA 4, 0x021b0810, 0x001F001F

+DATA 4, 0x021b480c, 0x001F001F

+DATA 4, 0x021b4810, 0x001F001F

+DATA 4, 0x021b083c, 0x43270338

+DATA 4, 0x021b0840, 0x03200314

+DATA 4, 0x021b483c, 0x431A032F

+DATA 4, 0x021b4840, 0x03200263

+DATA 4, 0x021b0848, 0x4B434748

+DATA 4, 0x021b4848, 0x4445404C

+DATA 4, 0x021b0850, 0x38444542

+DATA 4, 0x021b4850, 0x4935493A

+DATA 4, 0x021b081c, 0x33333333

+DATA 4, 0x021b0820, 0x33333333

+DATA 4, 0x021b0824, 0x33333333

+DATA 4, 0x021b0828, 0x33333333

+DATA 4, 0x021b481c, 0x33333333

+DATA 4, 0x021b4820, 0x33333333

+DATA 4, 0x021b4824, 0x33333333

+DATA 4, 0x021b4828, 0x33333333

+DATA 4, 0x021b08b8, 0x00000800

+DATA 4, 0x021b48b8, 0x00000800

+DATA 4, 0x021b0004, 0x00020036

+DATA 4, 0x021b0008, 0x09444040

+DATA 4, 0x021b000c, 0x898E7974

+DATA 4, 0x021b0010, 0xDB538F64

+DATA 4, 0x021b0014, 0x01FF00DB

+DATA 4, 0x021b0018, 0x00081740

+DATA 4, 0x021b001c, 0x00008000

+DATA 4, 0x021b002c, 0x000026d2

+DATA 4, 0x021b0030, 0x008E1023

+DATA 4, 0x021b0040, 0x00000047

+DATA 4, 0x021b0000, 0x841A0000

+DATA 4, 0x021b001c, 0x04088032

+DATA 4, 0x021b001c, 0x00008033

+DATA 4, 0x021b001c, 0x00428031

+DATA 4, 0x021b001c, 0x19308030

+DATA 4, 0x021b001c, 0x04008040

+DATA 4, 0x021b0020, 0x00007800

+DATA 4, 0x021b0818, 0x00022227

+DATA 4, 0x021b4818, 0x00022227

+DATA 4, 0x021b0004, 0x00025576

+DATA 4, 0x021b0404, 0x00011006

+DATA 4, 0x021b001c, 0x00000000

+

+/* set the default clock gate to save power */

+DATA 4, 0x020c4068, 0x00C03F3F

+DATA 4, 0x020c406c, 0x0030FC03

+DATA 4, 0x020c4070, 0x0FFFC000

+DATA 4, 0x020c4074, 0x3FF00000

+DATA 4, 0x020c4078, 0x00FFF300

+DATA 4, 0x020c407c, 0x0F0000F3

+DATA 4, 0x020c4080, 0x000003FF

+

+/* enable AXI cache for VDOA/VPU/IPU */

+DATA 4, 0x020e0010, 0xF00000CF

+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */

+DATA 4, 0x020e0018, 0x007F007F

+DATA 4, 0x020e001c, 0x007F007F

+

+/*

+ * Setup CCM_CCOSR register as follows:

+ *

+ * cko1_en  = 1	   --> CKO1 enabled

+ * cko1_div = 111  --> divide by 8

+ * cko1_sel = 1011 --> ahb_clk_root

+ *

+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz

+ */

+DATA 4, 0x020c4060, 0x000000fb