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author | Ye Li <ye.li@nxp.com> | 2016-07-28 11:42:14 +0800 |
---|---|---|
committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:04:43 +0800 |
commit | 70bc3dd2c40a5c5479b4aae6037e7914061a524e (patch) | |
tree | 9ca778dac58ecc6f88efc72ea3a35393fbf70d7d /board | |
parent | 4976f8f1adc5518135f663ef33991151be9d5067 (diff) | |
download | u-boot-imx-70bc3dd2c40a5c5479b4aae6037e7914061a524e.zip u-boot-imx-70bc3dd2c40a5c5479b4aae6037e7914061a524e.tar.gz u-boot-imx-70bc3dd2c40a5c5479b4aae6037e7914061a524e.tar.bz2 |
MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATA
We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fd8fbf7fa0b10199ac89cd13cae851149f51accb)
Diffstat (limited to 'board')
-rw-r--r-- | board/freescale/mx6qsabreauto/mx6qsabreauto.c | 9 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 9 |
2 files changed, 14 insertions, 4 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 2360c63..2c7b096 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -463,13 +463,11 @@ static void setup_fec(void) ret = enable_fec_anatop_clock(0, ENET_125MHZ); if (ret) printf("Error fec anatop clock settings!\n"); - - setup_iomux_enet(); } int board_eth_init(bd_t *bis) { - setup_fec(); + setup_iomux_enet(); return cpu_eth_init(bis); } @@ -715,6 +713,11 @@ int board_init(void) #ifdef CONFIG_MTD_NOR_FLASH setup_iomux_eimnor(); #endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; } diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index ee796bc..681de0d 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -800,7 +800,7 @@ int overwrite_console(void) return 1; } -int board_eth_init(bd_t *bis) +static void setup_fec(void) { if (is_mx6dqp()) { int ret; @@ -811,7 +811,10 @@ int board_eth_init(bd_t *bis) if (ret) printf("Error fec anatop clock settings!\n"); } +} +int board_eth_init(bd_t *bis) +{ setup_iomux_enet(); return cpu_eth_init(bis); @@ -920,6 +923,10 @@ int board_init(void) setup_sata(); #endif +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; } |