Merge branch 'master' of /home/wd/git/u-boot/custodians

23 files changed, 348 insertions, 566 deletions

diff --git a/board/atum8548/law.c b/board/atum8548/law.c
index b70b091..724b1bf 100644
--- a/board/atum8548/law.c
+++ b/board/atum8548/law.c
@@ -49,7 +49,7 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index 31614d2..1f11563 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -31,11 +31,11 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index f5644e1..4640c1d 100644
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
index 317ba26..3d308c8 100644
--- a/board/freescale/mpc8544ds/law.c
+++ b/board/freescale/mpc8544ds/law.c
@@ -30,10 +30,10 @@
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	/* contains both PCIE3 MEM & IO space */
 	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
index f5644e1..4640c1d 100644
--- a/board/freescale/mpc8560ads/law.c
+++ b/board/freescale/mpc8560ads/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index 02ea0ec..e13bb53 100644
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -29,11 +29,11 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index c69934c..933dd12 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -160,189 +160,105 @@ static struct pci_controller pcie2_hose;
 static struct pci_controller pcie3_hose;
 #endif
 
-int first_free_busno=0;
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+	struct fsl_pci_info pci_info[3];
+	u32 devdisr, pordevsr, io_sel, host_agent, temp32;
+	int first_free_busno = 0;
+	int num = 0;
+
+	int pcie_ep, pcie_configured;
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
 
 	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 			devdisr, io_sel, host_agent);
 
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 		printf ("    eTSEC1 is in sgmii mode.\n");
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 		printf ("    eTSEC2 is in sgmii mode.\n");
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 		printf ("    eTSEC3 is in sgmii mode.\n");
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 		printf ("    eTSEC4 is in sgmii mode.\n");
 
-
+	puts("\n");
 #ifdef CONFIG_PCIE3
-	{
-		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
-		struct pci_controller *hose = &pcie3_hose;
-		int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
-		int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
-		struct pci_region *r = hose->regions;
-		u32 temp32;
-
-		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-			printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
-					pcie_ep ? "End Point" : "Root Complex",
-					(uint)pci);
-			if (pci->pme_msg_det) {
-				pci->pme_msg_det = 0xffffffff;
-				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
-			}
-			printf ("\n");
-
-			/* outbound memory */
-			pci_set_region(r++,
-					CONFIG_SYS_PCIE3_MEM_BUS,
-					CONFIG_SYS_PCIE3_MEM_PHYS,
-					CONFIG_SYS_PCIE3_MEM_SIZE,
-					PCI_REGION_MEM);
-
-			/* outbound io */
-			pci_set_region(r++,
-					CONFIG_SYS_PCIE3_IO_BUS,
-					CONFIG_SYS_PCIE3_IO_PHYS,
-					CONFIG_SYS_PCIE3_IO_SIZE,
-					PCI_REGION_IO);
-
-			hose->region_count = r - hose->regions;
-			hose->first_busno=first_free_busno;
-
-			fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-			first_free_busno=hose->last_busno+1;
-			printf ("    PCIE3 on bus %02x - %02x\n",
-					hose->first_busno,hose->last_busno);
-
-			/*
-			 * Activate ULI1575 legacy chip by performing a fake
-			 * memory access.  Needed to make ULI RTC work.
-			 * Device 1d has the first on-board memory BAR.
-			 */
-
-			pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
-					PCI_BASE_ADDRESS_1, &temp32);
-			if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
-				void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
-								temp32, 4, 0);
-				debug(" uli1572 read to %p\n", p);
-				in_be32(p);
-			}
-		} else {
-			printf ("    PCIE3: disabled\n");
+	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+		SET_STD_PCIE_INFO(pci_info[num], 3);
+		printf ("    PCIE3 connected to ULI as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie3_hose, first_free_busno);
+		/*
+		 * Activate ULI1575 legacy chip by performing a fake
+		 * memory access.  Needed to make ULI RTC work.
+		 * Device 1d has the first on-board memory BAR.
+		 */
+		pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
+				PCI_BASE_ADDRESS_1, &temp32);
+		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
+			void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+					temp32, 4, 0);
+			debug(" uli1572 read to %p\n", p);
+			in_be32(p);
 		}
-
+	} else {
+		printf ("    PCIE3: disabled\n");
 	}
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE2
-	{
-		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-		struct pci_controller *hose = &pcie2_hose;
-		int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
-		int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
-		struct pci_region *r = hose->regions;
-
-		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
-			printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
-					pcie_ep ? "End Point" : "Root Complex",
-					(uint)pci);
-			if (pci->pme_msg_det) {
-				pci->pme_msg_det = 0xffffffff;
-				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
-			}
-			printf ("\n");
-
-			/* outbound memory */
-			pci_set_region(r++,
-					CONFIG_SYS_PCIE2_MEM_BUS,
-					CONFIG_SYS_PCIE2_MEM_PHYS,
-					CONFIG_SYS_PCIE2_MEM_SIZE,
-					PCI_REGION_MEM);
-
-			/* outbound io */
-			pci_set_region(r++,
-					CONFIG_SYS_PCIE2_IO_BUS,
-					CONFIG_SYS_PCIE2_IO_PHYS,
-					CONFIG_SYS_PCIE2_IO_SIZE,
-					PCI_REGION_IO);
-
-			hose->region_count = r - hose->regions;
-			hose->first_busno=first_free_busno;
-
-			fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-			first_free_busno=hose->last_busno+1;
-			printf ("    PCIE2 on bus %02x - %02x\n",
-					hose->first_busno,hose->last_busno);
-
-		} else {
-			printf ("    PCIE2: disabled\n");
-		}
-
+	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		printf ("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie2_hose, first_free_busno);
+	} else {
+		printf ("    PCIE2: disabled\n");
 	}
+
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
 #endif
-#ifdef CONFIG_PCIE1
-	{
-		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-		struct pci_controller *hose = &pcie1_hose;
-		int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
-		int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-		struct pci_region *r = hose->regions;
-
-		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-			printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
-					pcie_ep ? "End Point" : "Root Complex",
-					(uint)pci);
-			if (pci->pme_msg_det) {
-				pci->pme_msg_det = 0xffffffff;
-				debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
-			}
-			printf ("\n");
-
-			/* outbound memory */
-			pci_set_region(r++,
-					CONFIG_SYS_PCIE1_MEM_BUS,
-					CONFIG_SYS_PCIE1_MEM_PHYS,
-					CONFIG_SYS_PCIE1_MEM_SIZE,
-					PCI_REGION_MEM);
-
-			/* outbound io */
-			pci_set_region(r++,
-					CONFIG_SYS_PCIE1_IO_BUS,
-					CONFIG_SYS_PCIE1_IO_PHYS,
-					CONFIG_SYS_PCIE1_IO_SIZE,
-					PCI_REGION_IO);
-
-			hose->region_count = r - hose->regions;
-			hose->first_busno=first_free_busno;
-
-			fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-			first_free_busno=hose->last_busno+1;
-			printf("    PCIE1 on bus %02x - %02x\n",
-					hose->first_busno,hose->last_busno);
-
-		} else {
-			printf ("    PCIE1: disabled\n");
-		}
 
+#ifdef CONFIG_PCIE1
+	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		printf ("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
+	} else {
+		printf ("    PCIE1: disabled\n");
 	}
+
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 #endif
 }
 #endif
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 98111eb..358148f 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -387,19 +387,7 @@ void pci_init_board(void)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-			     "timebase-frequency", bd->bi_busfreq / 4, 1);
-	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-			     "bus-frequency", bd->bi_busfreq, 1);
-	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-			     "clock-frequency", bd->bi_intfreq, 1);
-	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
-			     "bus-frequency", bd->bi_busfreq, 1);
-
-	do_fixup_by_compat_u32(blob, "ns16550",
-			       "clock-frequency", bd->bi_busfreq, 1);
-
-	fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
+	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_PCI1
 	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index d1e659b..37c4b0a 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -23,10 +23,13 @@
 #include <common.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 				   unsigned int ctrl_num);
 
@@ -203,24 +206,40 @@ phys_size_t fixed_sdram (void)
 {
 	sys_info_t sysinfo;
 	char buf[32];
+	fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
+	size_t ddr_size;
+	struct cpu_type *cpu;
 
 	get_sys_info(&sysinfo);
 	printf("Configuring DDR for %s MT/s data rate\n",
 				strmhz(buf, sysinfo.freqDDRBus));
 
 	if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
-		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0);
+		ddr_cfg_regs = &ddr_cfg_regs_400;
 	else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
-		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0);
+		ddr_cfg_regs = &ddr_cfg_regs_533;
 	else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
-		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0);
+		ddr_cfg_regs = &ddr_cfg_regs_667;
 	else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
-		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
+		ddr_cfg_regs = &ddr_cfg_regs_800;
 	else
 		panic("Unsupported DDR data rate %s MT/s data rate\n",
 					strmhz(buf, sysinfo.freqDDRBus));
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	cpu = gd->cpu;
+	/* P1020 and it's derivatives support max 32bit DDR width */
+	if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
+		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+		ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+		ddr_cfg_regs->cs[0].bnds = 0x0000001F;
+		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+	}
+	else
+		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
+
+	return ddr_size;
 }
 
 phys_size_t initdram(int board_type)
diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
index 12d2bf4..1320d5d 100644
--- a/board/freescale/p1_p2_rdb/law.c
+++ b/board/freescale/p1_p2_rdb/law.c
@@ -26,9 +26,9 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index a3617d5..4c08f9e 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -41,60 +41,62 @@ static struct pci_controller pcie2_hose;
 
 void pci_init_board(void)
 {
-	struct fsl_pci_info pci_info[2];
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	uint devdisr = in_be32(&gur->devdisr);
-	uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-	uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
-	int num = 0;
+	struct fsl_pci_info pci_info[2];
+	u32 devdisr, pordevsr, io_sel, host_agent;
 	int first_free_busno = 0;
+	int num = 0;
 
 	int pcie_ep, pcie_configured;
 
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+
 	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 			devdisr, io_sel, host_agent);
 
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 		printf ("    eTSEC2 is in sgmii mode.\n");
 
+	puts("\n");
 #ifdef CONFIG_PCIE2
-	SET_STD_PCIE_INFO(pci_info[num], 2);
 	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
 	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		puts ("\n    PCIE2 connected to Slot 1 as ");
-		printf ("%s (base address %lx)",
-			pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num],
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		printf("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
-		num++;
 	} else {
 		printf ("    PCIE2: disabled\n");
 	}
+	puts("\n");
 #else
-	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE1
-	SET_STD_PCIE_INFO(pci_info[num], 1);
-
 	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
 	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		puts ("\n    PCIE1 connected to Slot 2 as ");
-		printf ("%s (base address %lx)",
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
 				pcie_ep ? "End Point" : "Root Complex",
 				pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num],
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie1_hose, first_free_busno);
-		num++;
 	} else {
 		printf ("    PCIE1: disabled\n");
 	}
+	puts("\n");
 #else
-	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 #endif
 }
 
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
index da297c5..28ed2ed 100644
--- a/board/freescale/p2020ds/law.c
+++ b/board/freescale/p2020ds/law.c
@@ -29,11 +29,11 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 7ad9be8..e38c014 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -192,69 +192,42 @@ static struct pci_controller pcie2_hose;
 static struct pci_controller pcie3_hose;
 #endif
 
-int first_free_busno = 0;
-
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+	struct fsl_pci_info pci_info[3];
+	u32 devdisr, pordevsr, io_sel, host_agent;
+	int first_free_busno = 0;
+	int num = 0;
 
-	volatile ccsr_fsl_pci_t *pci;
-	struct pci_controller *hose;
 	int pcie_ep, pcie_configured;
-	struct pci_region *r;
-/*		u32 temp32; */
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
 
 	debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 			devdisr, io_sel, host_agent);
 
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 		printf("    eTSEC2 is in sgmii mode.\n");
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 		printf("    eTSEC3 is in sgmii mode.\n");
 
+	puts("\n");
 #ifdef CONFIG_PCIE2
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	hose = &pcie2_hose;
 	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
 	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
-	r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
-		printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		printf("    PCIE2 connected to ULI as %s (base addr %lx)\n",
 				pcie_ep ? "End Point" : "Root Complex",
-				(uint)pci);
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				pci->pme_msg_det);
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE2_MEM_BUS,
-				CONFIG_SYS_PCIE2_MEM_PHYS,
-				CONFIG_SYS_PCIE2_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE2_IO_BUS,
-				CONFIG_SYS_PCIE2_IO_PHYS,
-				CONFIG_SYS_PCIE2_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		first_free_busno = hose->last_busno+1;
-		printf("    PCIE2 on bus %02x - %02x\n",
-			hose->first_busno, hose->last_busno);
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie2_hose, first_free_busno);
 
 		/*
 		 * The workaround doesn't work on p2020 because the location
@@ -279,104 +252,47 @@ void pci_init_board(void)
 	} else {
 		printf("    PCIE2: disabled\n");
 	}
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE3
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
-	hose = &pcie3_hose;
 	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
 	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
-	r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
-		printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
+		SET_STD_PCIE_INFO(pci_info[num], 3);
+		printf("    PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
 				pcie_ep ? "End Point" : "Root Complex",
-				(uint)pci);
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				pci->pme_msg_det);
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE3_MEM_BUS,
-				CONFIG_SYS_PCIE3_MEM_PHYS,
-				CONFIG_SYS_PCIE3_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE3_IO_BUS,
-				CONFIG_SYS_PCIE3_IO_PHYS,
-				CONFIG_SYS_PCIE3_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		first_free_busno = hose->last_busno+1;
-		printf("    PCIE3 on bus %02x - %02x\n",
-				hose->first_busno, hose->last_busno);
-
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie3_hose, first_free_busno);
 	} else {
 		printf("    PCIE3: disabled\n");
 	}
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE1
-	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	hose = &pcie1_hose;
 	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
 	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-	r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
-		printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
 				pcie_ep ? "End Point" : "Root Complex",
-				(uint)pci);
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug(" with errors.  Clearing.  Now 0x%08x",
-				pci->pme_msg_det);
-		}
-		printf("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_MEM_BUS,
-				CONFIG_SYS_PCIE1_MEM_PHYS,
-				CONFIG_SYS_PCIE1_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-				CONFIG_SYS_PCIE1_IO_BUS,
-				CONFIG_SYS_PCIE1_IO_PHYS,
-				CONFIG_SYS_PCIE1_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		first_free_busno = hose->last_busno+1;
-		printf("    PCIE1 on bus %02x - %02x\n",
-			hose->first_busno, hose->last_busno);
-
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
 	} else {
 		printf("    PCIE1: disabled\n");
 	}
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 #endif
 }
 #endif
diff --git a/board/pm854/law.c b/board/pm854/law.c
index 39e8dbb..ac21d7a 100644
--- a/board/pm854/law.c
+++ b/board/pm854/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/pm856/law.c b/board/pm856/law.c
index 39e8dbb..ac21d7a 100644
--- a/board/pm856/law.c
+++ b/board/pm856/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
index 9919a6e..09e5c2e 100644
--- a/board/sbc8548/Makefile
+++ b/board/sbc8548/Makefile
@@ -2,8 +2,8 @@
 # (C) Copyright 2004-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
-# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
-# Added support for Wind River SBC8560 board
+# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8548 board
 #
 # See file CREDITS for list of people who contributed to this
 # project.
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index e8c7ae2..6d1efc0 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -32,8 +32,10 @@
  *
  * 0x0000_0000	0x0fff_ffff	DDR			256M
  * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M
+ * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M
  * 0xe000_0000	0xe000_ffff	CCSR			1M
- * 0xe200_0000	0xe2ff_ffff	PCI1 IO			16M
+ * 0xe200_0000	0xe27f_ffff	PCI1 IO			8M
+ * 0xe280_0000	0xe2ff_ffff	PCIe IO			8M
  * 0xf000_0000	0xf7ff_ffff	SDRAM			128M
  * 0xf8b0_0000	0xf80f_ffff	EEPROM			1M
  * 0xfb80_0000	0xff7f_ffff	FLASH (2nd bank)	64M
@@ -48,8 +50,14 @@ struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+#endif
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e5b21b5..194f6ab 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -1,5 +1,6 @@
 /*
- * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
+ *
  * Copyright 2007 Embedded Specialties, Inc.
  *
  * Copyright 2004, 2007 Freescale Semiconductor.
@@ -32,6 +33,8 @@
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <spd_sdram.h>
+#include <netdev.h>
+#include <tsec.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -49,25 +52,19 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
 
 	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
-			(*rev) >> 4);
+			in_8(rev) >> 4);
 
 	/*
 	 * Initialize local bus.
 	 */
 	local_bus_init ();
 
-	/*
-	 * Hack TSEC 3 and 4 IO voltages.
-	 */
-	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
-
-	ecm->eedr = 0xffffffff;		/* clear ecm errors */
-	ecm->eeer = 0xffffffff;		/* enable ecm errors */
+	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
 	return 0;
 }
 
@@ -89,7 +86,7 @@ initdram(int board_type)
 
 		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
-		gur->ddrdllcr = 0x81000000;
+		out_be32(&gur->ddrdllcr, 0x81000000);
 		asm("sync;isync;msync");
 		udelay(200);
 	}
@@ -126,24 +123,24 @@ local_bus_init(void)
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
-	gur->lbiuiplldcr1 = 0x00078080;
+	out_be32(&gur->lbiuiplldcr1, 0x00078080);
 	if (clkdiv == 16) {
-		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
 	} else if (clkdiv == 8) {
-		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
 	} else if (clkdiv == 4) {
-		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
 	}
 
-	lbc->lcrr |= 0x00030000;
+	setbits_be32(&lbc->lcrr, 0x00030000);
 
 	asm("sync;isync;msync");
 
-	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
-	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
+	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
+	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
 }
 
 /*
@@ -152,7 +149,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 
 	uint idx;
 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -166,18 +163,24 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or3 = CONFIG_SYS_OR3_PRELIM;
+	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
 	asm("msync");
 
-	lbc->br3 = CONFIG_SYS_BR3_PRELIM;
+	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
 	asm("msync");
 
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
 	asm("msync");
 
+	out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
+	asm("msync");
 
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+	asm("msync");
+
+
+	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
+	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	asm("msync");
 
 	/*
@@ -189,7 +192,7 @@ sdram_init(void)
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -199,7 +202,7 @@ sdram_init(void)
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -209,7 +212,7 @@ sdram_init(void)
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -218,7 +221,7 @@ sdram_init(void)
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -266,228 +269,132 @@ testdram(void)
 }
 #endif
 
-#if	!defined(CONFIG_SPD_EEPROM)
+#if !defined(CONFIG_SPD_EEPROM)
+#define CONFIG_SYS_DDR_CONTROL 0xc300c000
 /*************************************************************************
  *  fixed_sdram init -- doesn't use serial presence detect.
  *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
  ************************************************************************/
 long int fixed_sdram (void)
 {
-    #define CONFIG_SYS_DDR_CONTROL 0xc300c000
-
 	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds		= 0x0000007f;
-	ddr->cs1_bnds		= 0x008000ff;
-	ddr->cs2_bnds		= 0x00000000;
-	ddr->cs3_bnds		= 0x00000000;
-	ddr->cs0_config		= 0x80010101;
-	ddr->cs1_config		= 0x80010101;
-	ddr->cs2_config		= 0x00000000;
-	ddr->cs3_config		= 0x00000000;
-	ddr->timing_cfg_3		= 0x00000000;
-	ddr->timing_cfg_0	= 0x00220802;
-	ddr->timing_cfg_1	= 0x38377322;
-	ddr->timing_cfg_2	= 0x0fa044C7;
-	ddr->sdram_cfg		= 0x4300C000;
-	ddr->sdram_cfg_2	= 0x24401000;
-	ddr->sdram_mode		= 0x23C00542;
-	ddr->sdram_mode_2	= 0x00000000;
-	ddr->sdram_interval	= 0x05080100;
-	ddr->sdram_md_cntl	= 0x00000000;
-	ddr->sdram_data_init	= 0x00000000;
-	ddr->sdram_clk_cntl	= 0x03800000;
+	out_be32(&ddr->cs0_bnds, 0x0000007f);
+	out_be32(&ddr->cs1_bnds, 0x008000ff);
+	out_be32(&ddr->cs2_bnds, 0x00000000);
+	out_be32(&ddr->cs3_bnds, 0x00000000);
+	out_be32(&ddr->cs0_config, 0x80010101);
+	out_be32(&ddr->cs1_config, 0x80010101);
+	out_be32(&ddr->cs2_config, 0x00000000);
+	out_be32(&ddr->cs3_config, 0x00000000);
+	out_be32(&ddr->timing_cfg_3, 0x00000000);
+	out_be32(&ddr->timing_cfg_0, 0x00220802);
+	out_be32(&ddr->timing_cfg_1, 0x38377322);
+	out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
+	out_be32(&ddr->sdram_cfg, 0x4300C000);
+	out_be32(&ddr->sdram_cfg_2, 0x24401000);
+	out_be32(&ddr->sdram_mode, 0x23C00542);
+	out_be32(&ddr->sdram_mode_2, 0x00000000);
+	out_be32(&ddr->sdram_interval, 0x05080100);
+	out_be32(&ddr->sdram_md_cntl, 0x00000000);
+	out_be32(&ddr->sdram_data_init, 0x00000000);
+	out_be32(&ddr->sdram_clk_cntl, 0x03800000);
 	asm("sync;isync;msync");
 	udelay(500);
 
 	#if defined (CONFIG_DDR_ECC)
 	  /* Enable ECC checking */
-	  ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
 	#else
-	  ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
 	#endif
 
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif
 
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device.  Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_sbc8548_config_table[] = {
-	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
-		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
-		mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
-		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
-		mpc85xx_config_via_ac97, {0,0,0}},
-	{},
-};
-
-static struct pci_controller pci1_hose = {
-	config_table: pci_sbc8548_config_table};
-#endif	/* CONFIG_PCI */
-
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif	/* CONFIG_PCI2 */
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif	/* CONFIG_PCI1 */
 
 #ifdef CONFIG_PCIE1
 static struct pci_controller pcie1_hose;
 #endif	/* CONFIG_PCIE1 */
 
-int first_free_busno=0;
 
+#ifdef CONFIG_PCI
 void
 pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info[2];
+	u32 devdisr, pordevsr, porpllsr, io_sel;
+	int first_free_busno = 0;
+	int num = 0;
 
-#ifdef CONFIG_PCI1
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-	struct pci_controller *hose = &pci1_hose;
-	struct pci_config_table *table;
-	struct pci_region *r = hose->regions;
+#ifdef CONFIG_PCIE1
+	int pcie_configured;
+#endif
 
-	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
-	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
-	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 
-	uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
+	debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
-	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+#ifdef CONFIG_PCI1
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */
 
-	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
-		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
+		printf ("    PCI host: %d bit, %s MHz, %s, %s\n",
 			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
+			(pci_speed == 33000000) ? "33" :
+			(pci_speed == 66000000) ? "66" : "unknown",
 			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter"
-			);
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
-			       CONFIG_SYS_PCI1_MEM_PHYS,
-			       CONFIG_SYS_PCI1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BASE,
-			       CONFIG_SYS_PCI1_IO_PHYS,
-			       CONFIG_SYS_PCI1_IO_SIZE,
-			       PCI_REGION_IO);
-		hose->region_count = r - hose->regions;
-
-		/* relocate config table pointers */
-		hose->config_table = \
-			(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
-		for (table = hose->config_table; table && table->vendor; table++)
-			table->config_device += gd->reloc_off;
-
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		first_free_busno=hose->last_busno+1;
-		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
-#ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
-			/* PCI-X init */
-			if (CONFIG_SYS_CLK_FREQ < 66000000)
-				printf("PCI-X will only work at 66 MHz\n");
-
-			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
-				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
-			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
-		}
-#endif
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		SET_STD_PCI_INFO(pci_info[num], 1);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pci1_hose, first_free_busno);
 	} else {
 		printf ("    PCI: disabled\n");
 	}
-}
+
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 #endif
 
-#ifdef CONFIG_PCI2
-{
-	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
-	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
-	if (pci_dual) {
-		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
-			pci2_clk_sel ? "sync" : "async");
-	} else {
-		printf ("    PCI2: disabled\n");
-	}
-}
-#else
-	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
-#endif /* CONFIG_PCI2 */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
 
 #ifdef CONFIG_PCIE1
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pcie1_hose;
-	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
-	struct pci_region *r = hose->regions;
-
-	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
-	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
-		printf ("\n    PCIE connected to slot as %s (base address %x)",
-			pcie_ep ? "End Point" : "Root Complex",
-			(uint)pci);
-
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
-		}
-		printf ("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
-			       CONFIG_SYS_PCIE1_MEM_PHYS,
-			       CONFIG_SYS_PCIE1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BASE,
-			       CONFIG_SYS_PCIE1_IO_PHYS,
-			       CONFIG_SYS_PCIE1_IO_SIZE,
-			       PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
-
-		first_free_busno=hose->last_busno+1;
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		printf ("    PCIE at base address %lx\n", pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
 	} else {
 		printf ("    PCIE: disabled\n");
 	}
- }
+
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+}
 #endif
 
+int board_eth_init(bd_t *bis)
+{
+	tsec_standard_init(bis);
+	pci_eth_init(bis);
+	return 0;	/* otherwise cpu_eth_init gets run */
 }
 
 int last_stage_init(void)
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 18d11f6..38bdeb3 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -31,65 +31,73 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff800000	16M	TLB for 8MB FLASH
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	56M	8MB -> 64MB of user flash
+	 * 0xff800000	8M	boot FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
+		      CONFIG_SYS_ALT_FLASH + 0x800000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_16M, 1),
+		      0, 0, BOOKE_PAGESZ_64M, 1),
 
 	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	512M	PCI1 MEM
+	 * 0xa0000000	512M	PCIe MEM
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
+		      0, 1, BOOKE_PAGESZ_1G, 1),
 
 	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M Cacheable, non-guarded
+	 * TLB 2:	256M Cacheable, non-guarded
 	 * 0x0		256M DDR SDRAM
 	 */
-	#if !defined(CONFIG_SPD_EEPROM)
+#if !defined(CONFIG_SPD_EEPROM)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-	#endif
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+#endif
 
 	/*
-	 * TLB 4:	64M	Non-cacheable, guarded
+	 * TLB 3:	64M	Non-cacheable, guarded
 	 * 0xe0000000	1M	CCSRBAR
-	 * 0xe2000000	16M	PCI1 IO
+	 * 0xe2000000	8M	PCI1 IO
+	 * 0xe2800000	8M	PCIe IO
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 4:	64M	Cacheable, non-guarded
+	 * 0xf0000000	64M	LBC SDRAM First half
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 
 	/*
 	 * TLB 5:	64M	Cacheable, non-guarded
-	 * 0xf0000000	64M	LBC SDRAM
+	 * 0xf4000000	64M	LBC SDRAM Second half
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -103,6 +111,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
+
+	/*
+	 * TLB 7:	4M	Non-cacheable, guarded
+	 * 0xfb800000	4M	1st 4MB block of 64MB user FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_4M, 1),
+
+	/*
+	 * TLB 8:	4M	Non-cacheable, guarded
+	 * 0xfbc00000	4M	2nd 4MB block of 64MB user FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
+		      CONFIG_SYS_ALT_FLASH + 0x400000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_4M, 1),
+
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/socrates/law.c b/board/socrates/law.c
index 71cff8c..cb55fd4 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -52,9 +52,9 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #if defined(CONFIG_SYS_FPGA_BASE)
-	SET_LAW(CONFIG_SYS_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-	SET_LAW(CONFIG_SYS_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stx/stxgp3/law.c b/board/stx/stxgp3/law.c
index ba89f0e..af0ac09 100644
--- a/board/stx/stxgp3/law.c
+++ b/board/stx/stxgp3/law.c
@@ -52,7 +52,7 @@ struct law_entry law_table[] = {
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stx/stxssa/law.c b/board/stx/stxssa/law.c
index 55dde66..e3c34ed 100644
--- a/board/stx/stxssa/law.c
+++ b/board/stx/stxssa/law.c
@@ -54,7 +54,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
 	/* Map the whole localbus, including flash and reset latch. */
-	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c
index 386f9c5..bbfcb9d 100644
--- a/board/xes/xpedite5200/law.c
+++ b/board/xes/xpedite5200/law.c
@@ -40,7 +40,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #if CONFIG_SYS_PCI1_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
 #endif
 #if CONFIG_SYS_PCI2_MEM_PHYS
 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),