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authorWolfgang Denk <wd@denx.de>2011-11-08 07:44:52 +0100
committerWolfgang Denk <wd@denx.de>2011-11-08 07:44:52 +0100
commit5721385b187b3154c7768e6c182501022f4e2e45 (patch)
tree539198587e4c6f6d03f2065bfebc4bb697773300 /board
parent688d8f33f27ea596efb6632388ee60360996eed0 (diff)
parent6be55ee2252c364b16d99537bf9fe7d96d5c77b4 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx: powerpc/mpc83xx: Add 33.33MHz support for mpc8360emds powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds mpc83xx: Rename CONFIG_SYS_DDR_CONFIG and cleanup DDR csbnds code mpc83xx: Cleanup usage of LBC constants mpc83xx: Cleanup usage of DDR constants mpc83xx: Cleanup usage of BAT constants mpc83xx: cosmetic: vme8349.h checkpatch compliance mpc83xx: cosmetic: ve8313.h checkpatch compliance mpc83xx: cosmetic: sbc8349.h checkpatch compliance mpc83xx: cosmetic: mpc8308_p1m.h checkpatch compliance mpc83xx: cosmetic: kmeter1.h checkpatch compliance mpc83xx: cosmetic: TQM834x.h checkpatch compliance mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance mpc83xx: cosmetic: MVBLM7.h checkpatch compliance mpc83xx: cosmetic: MPC837XERDB.h checkpatch compliance mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance mpc83xx: cosmetic: MPC8360ERDK.h checkpatch compliance mpc83xx: cosmetic: MPC8360EMDS.h checkpatch compliance mpc83xx: cosmetic: MPC8349ITX.h checkpatch compliance mpc83xx: cosmetic: MPC8349EMDS.h checkpatch compliance mpc83xx: cosmetic: MPC832XEMDS.h checkpatch compliance mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance mpc83xx: cosmetic: MPC8315ERDB.h checkpatch compliance mpc83xx: cosmetic: MPC8313ERDB.h checkpatch compliance mpc83xx: cosmetic: MPC8308RDB.h checkpatch compliance mpc83xx: cosmetic: MERGERBOX.h checkpatch compliance mpc83xx: Fix ipic structure definition powerpc, mpc83xx: add DDR SDRAM Timing Configuration 3 definitions cosmetic, powerpc, mpc83xx: checkpatch cleanup powerpc/83xx: move km 83xx specific i2c code to km83xx_i2c mpc83xx: fix global timer structure definition
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mpc8313erdb/sdram.c10
-rw-r--r--board/freescale/mpc8349emds/mpc8349emds.c27
-rw-r--r--board/freescale/mpc8349itx/mpc8349itx.c28
-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c69
-rw-r--r--board/keymile/common/common.c71
-rw-r--r--board/keymile/common/common.h3
-rw-r--r--board/keymile/km83xx/Makefile2
-rw-r--r--board/keymile/km83xx/km83xx_i2c.c88
-rw-r--r--board/sbc8349/sbc8349.c27
-rw-r--r--board/ve8313/ve8313.c10
10 files changed, 208 insertions, 127 deletions
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 7aede13..a9a2ba4 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -74,8 +74,14 @@ static long fixed_sdram(void)
*/
__udelay(50000);
- im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA);
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
/* Currently we use only one CS, so disable the other bank. */
im->ddr.cs_config[1] = 0;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 620540f..ebd5274 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -101,18 +101,10 @@ phys_size_t initdram (int board_type)
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size>>1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20; /* DDR size in bytes */
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
@@ -133,8 +125,15 @@ int fixed_sdram(void)
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
- im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[2].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 5647579..9cc808e 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -43,23 +43,27 @@
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 ddr_size; /* The size of RAM, in bytes */
- u32 ddr_size_log2 = 0;
-
- for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
- if (ddr_size & 1) {
- return -1;
- }
- ddr_size_log2++;
- }
+ /* The size of RAM, in bytes */
+ u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
+ u32 ddr_size_log2 = __ilog2(ddr_size);
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- /* Only one CS0 for DDR */
- im->ddr.csbnds[0].csbnds = 0x0000000f;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ /* Only one CS for DDR */
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[2] = 0;
+ im->ddr.cs_config[3] = 0;
debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 51d8035..be76774 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@@ -24,6 +24,7 @@
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
+#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@@ -139,9 +140,20 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
+ gd_t *gd;
#ifdef CONFIG_PQ_MDS_PIB
pib_init();
#endif
+ /*
+ * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
+ * So re-setup PCI MEM space used BAT5 after relocated to DDR
+ */
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+ write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
+ write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
+ }
+
return 0;
}
@@ -216,19 +228,15 @@ phys_size_t initdram(int board_type)
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20;
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+ u32 half_ddr_size = ddr_size >> 1;
+
+ im->sysconf.ddrlaw[0].bar =
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
@@ -246,11 +254,25 @@ int fixed_sdram(void)
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
- im->ddr.csbnds[0].csbnds = 0x00000007;
- im->ddr.csbnds[1].csbnds = 0x0008000f;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
- im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.csbnds[1].csbnds =
+ (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
+ CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
+
+ im->ddr.cs_config[2] = 0;
+ im->ddr.cs_config[3] = 0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
@@ -292,6 +314,19 @@ static int sdram_init(unsigned int base)
if (rem)
base = base - rem + sdram_size;
+ /*
+ * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
+ * After relocated to DDR, reuse BAT5 for PCI MEM space
+ */
+ if (base > CONFIG_MAX_MEM_MAPPED) {
+ unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
+ unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
+
+ /* Setup the BAT6 for SDRAM */
+ write_bat(DBAT6, batu, batl);
+ write_bat(IBAT6, batu, batl);
+ }
+
sdram_addr = (uint *)base;
/*
* Setup SDRAM Base and Option Registers
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 612dd2a..f262306 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -39,7 +39,10 @@
#include <i2c.h>
#endif
+#if !defined(CONFIG_MPC83xx)
static void i2c_write_start_seq(void);
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -89,9 +92,7 @@ int set_km_env(void)
return 0;
}
-#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
-#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
-
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
#if !defined(CONFIG_MPC83xx)
static void i2c_write_start_seq(void)
{
@@ -171,68 +172,6 @@ int i2c_make_abort(void)
#endif
return ret;
}
-#endif /* !MPC83xx */
-
-#if defined(CONFIG_MPC83xx)
-static void i2c_write_start_seq(void)
-{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
-}
-
-int i2c_make_abort(void)
-{
- struct fsl_i2c *dev;
- dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
- uchar dummy;
- uchar last;
- int nbr_read = 0;
- int i = 0;
- int ret = 0;
-
- /* wait after each operation to finsh with a delay */
- out_8(&dev->cr, (I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
- udelay(DELAY_ABORT_SEQ);
- dummy = in_8(&dev->dr);
- udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
- nbr_read++;
-
- /*
- * do read until the last bit is 1, but stop if the full eeprom is
- * read.
- */
- while (((last & 0x01) != 0x01) &&
- (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
- udelay(DELAY_ABORT_SEQ);
- last = in_8(&dev->dr);
- nbr_read++;
- }
- if ((last & 0x01) != 0x01)
- ret = -2;
- if ((last != 0xff) || (nbr_read > 1))
- printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
- nbr_read, last);
- udelay(DELAY_ABORT_SEQ);
- out_8(&dev->cr, (I2C_CR_MEN));
- udelay(DELAY_ABORT_SEQ);
- /* clear status reg */
- out_8(&dev->sr, 0);
-
- for (i = 0; i < 5; i++)
- i2c_write_start_seq();
- if (ret != 0)
- printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
- nbr_read, last);
-
- return ret;
-}
#endif
/**
@@ -244,6 +183,8 @@ void i2c_init_board(void)
/* Now run the AbortSequence() */
i2c_make_abort();
}
+#endif
+
#if !defined(MACH_TYPE_KM_KIRKWOOD)
int ethernet_present(void)
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 0fb19cf..6c1f640 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -136,6 +136,9 @@ int fdt_get_node_and_value(void *blob,
char *propname,
void **var);
+#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
+#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
+
int i2c_soft_read_pin(void);
int i2c_make_abort(void);
#endif /* __KEYMILE_COMMON_H */
diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile
index 72945e2..472768a 100644
--- a/board/keymile/km83xx/Makefile
+++ b/board/keymile/km83xx/Makefile
@@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS += $(BOARD).o ../common/common.o ../common/ivm.o
+COBJS += $(BOARD).o ../common/common.o ../common/ivm.o $(BOARD)_i2c.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c
new file mode 100644
index 0000000..be17775
--- /dev/null
+++ b/board/keymile/km83xx/km83xx_i2c.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <linux/ctype.h>
+#include "../common/common.h"
+
+static void i2c_write_start_seq(void)
+{
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN));
+}
+
+int i2c_make_abort(void)
+{
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ uchar dummy;
+ uchar last;
+ int nbr_read = 0;
+ int i = 0;
+ int ret = 0;
+
+ /* wait after each operation to finsh with a delay */
+ out_8(&dev->cr, (I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ dummy = in_8(&dev->dr);
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
+
+ /*
+ * do read until the last bit is 1, but stop if the full eeprom is
+ * read.
+ */
+ while (((last & 0x01) != 0x01) &&
+ (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
+ }
+ if ((last & 0x01) != 0x01)
+ ret = -2;
+ if ((last != 0xff) || (nbr_read > 1))
+ printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
+ nbr_read, last);
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN));
+ udelay(DELAY_ABORT_SEQ);
+ /* clear status reg */
+ out_8(&dev->sr, 0);
+
+ for (i = 0; i < 5; i++)
+ i2c_write_start_seq();
+ if (ret != 0)
+ printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
+ nbr_read, last);
+
+ return ret;
+}
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 50fae7c..42f4c1e 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -89,26 +89,25 @@ phys_size_t initdram (int board_type)
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size>>1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20; /* DDR size in bytes */
+ u32 ddr_size_log2 = __ilog2(msize);
+
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currently any ddr size other than 256 is not supported
#endif
- im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[2].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 166e459..924d871 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -65,8 +65,14 @@ static long fixed_sdram(void)
*/
__udelay(50000);
- out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ out_be32(&im->ddr.csbnds[0].csbnds,
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA));
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
/* Currently we use only one CS, so disable the other bank. */
out_be32(&im->ddr.cs_config[1], 0);