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authorWolfgang Denk <wd@denx.de>2009-06-14 20:58:46 +0200
committerWolfgang Denk <wd@denx.de>2009-07-14 00:01:58 +0200
commit0549353a6ba5aa03420c0962b9072e9cf1fa49d9 (patch)
treeed7d0b57833b2f0a2710b2702f02e7c908434e39 /board
parenta9905db5d29a56aedd7db5bcb56b0385873aa6a3 (diff)
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mecp5123: fix build error
The mecp5123 board did not compile because the MSCAN Clock Control Registers were missing; these got added, but as an array instead of 4 individual registers. Adapt the code so it builds. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Diffstat (limited to 'board')
-rw-r--r--board/esd/mecp5123/mecp5123.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index 909b458..bff96db 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -79,6 +79,7 @@ int board_early_init_f(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 spridr;
+ int i;
/*
* Initialize Local Window for NOR FLASH access
@@ -129,14 +130,10 @@ int board_early_init_f(void)
/*
* Configure MSCAN clocks
*/
- out_be32(&im->clk.m1ccr, 0x00300000);
- out_be32(&im->clk.m2ccr, 0x00300000);
- out_be32(&im->clk.m3ccr, 0x00300000);
- out_be32(&im->clk.m4ccr, 0x00300000);
- out_be32(&im->clk.m1ccr, 0x00310000);
- out_be32(&im->clk.m2ccr, 0x00310000);
- out_be32(&im->clk.m3ccr, 0x00310000);
- out_be32(&im->clk.m4ccr, 0x00310000);
+ for (i=0; i<4; ++i) {
+ out_be32(&im->clk.msccr[i], 0x00300000);
+ out_be32(&im->clk.msccr[i], 0x00310000);
+ }
/*
* Configure GPIO's