diff options
| author | Stefan Roese <sr@denx.de> | 2016-08-25 16:22:10 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-09-24 10:00:41 +0200 |
| commit | 9ed00b072be8fe346604eaec805359fa762fcb59 (patch) | |
| tree | 10108077efd7f646af40f62ccfdbe9e3450c794b /board | |
| parent | 8824cfc19a6e4ae23ca8006bb22b7b6f839b09a8 (diff) | |
| download | u-boot-imx-9ed00b072be8fe346604eaec805359fa762fcb59.zip u-boot-imx-9ed00b072be8fe346604eaec805359fa762fcb59.tar.gz u-boot-imx-9ed00b072be8fe346604eaec805359fa762fcb59.tar.bz2 | |
arm: mvebu: theadorable: Configure board for PCIe 2.0 capability
Use a board-specific board_sat_r_get() function to configure the board
for PCIe 2.0 capability (e.g. 5GB/s link speed). Otherwise the default
of 2.5GB/s will be established.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/theadorable/theadorable.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index c1db289..d621682 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -126,6 +126,12 @@ MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) return &theadorable_serdes_cfg[0]; } +u8 board_sat_r_get(u8 dev_num, u8 reg) +{ + /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */ + return 0x01; +} + int board_early_init_f(void) { /* Configure MPP */ |