MXSCM-290-2 mx6dqscm: convert to enable OF_CONTROL and DM drivers

Update mx6dqscm boards code and build configurations to enable
OF_CONTROL and DM drivers.

1. Update GPIO codes for adding gpio request
2. Enable USB DM driver
3. Update PMIC and LDO by-pass codes for DM PMIC
4. Add spinor boot support
5. Add lpddr2 modes, sizes and boards on local Kconfig
6. Update license with NXP 2017
7. Add defconfigs for qwks boards

Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>

7 files changed, 261 insertions, 90 deletions

diff --git a/board/freescale/mx6dqscm/Kconfig b/board/freescale/mx6dqscm/Kconfig
index d852d1e..d71145f 100644
--- a/board/freescale/mx6dqscm/Kconfig
+++ b/board/freescale/mx6dqscm/Kconfig
@@ -6,10 +6,41 @@ config SYS_BOARD
 config SYS_VENDOR
 	default "freescale"
 
-config SYS_SOC
-	default "mx6"
-
 config SYS_CONFIG_NAME
 	default "mx6dqscm"
 
+config QWKS_REV3
+	bool "Support for SCM QWKS rev3 board"
+	help
+	  Enable this when building for SCM QWKS board rev3 (revC).
+
+config SCMEVB
+	bool "Support for SCM EVB board"
+	help
+	  Enable this when building for SCM EVB board.
+
+config SCMHVB
+	bool "Support for Hardware Evaluation board"
+	help
+	  Enable this when building for SCM HVB board.
+
+config INTERLEAVING_MODE
+	bool "Interleaving mode"
+	help
+	  Enable the MMDC interlaving mode for lpddr2
+	  fix mode is used when this is not enabled.
+
+config SCM_LPDDR2_512MB
+	bool "lpddr2 size of 512MB"
+	help
+	  Set the lpddr2 size to 512 MB
+	  1GB is defaulted size.
+
+
+config SCM_LPDDR2_2GB
+	bool "lpddr2 size of 2GB"
+	help
+	  Set the lpddr2 size to 2GB
+	  1GB is defaulted size.
+
 endif
diff --git a/board/freescale/mx6dqscm/MAINTAINERS b/board/freescale/mx6dqscm/MAINTAINERS
index 31bd57d..7d23b7d 100644
--- a/board/freescale/mx6dqscm/MAINTAINERS
+++ b/board/freescale/mx6dqscm/MAINTAINERS
@@ -4,8 +4,11 @@ M:	Juan Gutierrez <juan.gutierrez@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6dqscm/
 F:	include/configs/mx6dqscm.h
-F:	configs/mx6dqscm_1gb_fix_evb_defconfig
-F:	configs/mx6dqscm_1gb_fix_qwks_rev2_defconfig
-F:	configs/mx6dqscm_1gb_fix_qwks_rev2_spinor_defconfig
-F:	configs/mx6dqscm_1gb_interleaving_evb_android_defconfig
-F:	configs/mx6dqscm_1gb_interleaving_qwks_rev2_android_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev2_android_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev2_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev2_plugin_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev2_spinor_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev3_android_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev3_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev3_plugin_defconfig
+F:	mx6dqscm_1gb_fix_qwks_rev3_spinor_defconfig
diff --git a/board/freescale/mx6dqscm/Makefile b/board/freescale/mx6dqscm/Makefile
index 5b8fb46..98f1457 100644
--- a/board/freescale/mx6dqscm/Makefile
+++ b/board/freescale/mx6dqscm/Makefile
@@ -1,11 +1,9 @@
 #
-# (C) Copyright 2016 Freescale Semiconductor, Inc.
+# Copyright (C) 2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
 #
 # SPDX-License-Identifier:  GPL-2.0+
 #
 
 obj-y  := mx6dqscm.o
 
-extra-$(CONFIG_USE_PLUGIN) :=  plugin.bin
-$(obj)/plugin.bin: $(obj)/plugin.o
-	$(OBJCOPY) -O binary --gap-fill 0xff $< $@
diff --git a/board/freescale/mx6dqscm/README b/board/freescale/mx6dqscm/README
index 7dec852..3737fd8 100644
--- a/board/freescale/mx6dqscm/README
+++ b/board/freescale/mx6dqscm/README
@@ -1,9 +1,9 @@
 How to use U-Boot on Freescale MX6DQSCM boards
 ----------------------------------------------
 
-- Build U-Boot for MX6DQSCM QWKS rev2 board*:
+- Build U-Boot for MX6DQSCM QWKS rev3 board*:
 
-$ make mx6dqscm_1gb_fix_qwks_rev2_defconfig
+$ make mx6dqscm_1gb_fix_qwks_rev3_defconfig
 $ make
 
 This will generate the u-boot image u-boot.imx.
@@ -13,9 +13,9 @@ This will generate the u-boot image u-boot.imx.
 sudo dd if=u-boot.imx of=/dev/sdX bs=1k seek=1; sync
 
 *Other defconfigs availabe are:
-    mx6dqscm_1gb_fix_qwks_rev2_defconfig
-    mx6dqscm_1gb_fix_qwks_rev2_spinor_defconfig
-    mx6dqscm_1gb_interleaving_qwks_rev2_android_defconfig
+    mx6dqscm_1gb_fix_qwks_rev3_defconfig
+    mx6dqscm_1gb_fix_qwks_rev3_spinor_defconfig
+    mx6dqscm_1gb_interleaving_qwks_rev3_android_defconfig
 
 
 - Jumper settings for fix mode images to boot from the top SD:
@@ -38,52 +38,26 @@ Single channel(epop)            SW1: ON  OFF OFF ON  ON  OFF ON  ON
 Additional configurations
 ==========================
 
-For custom configurations like 2GB or 512MB, the CONFIG_SYS_EXTRA_OPTIONS option on the defconfig
-file can be modified according to the customization needed.
+For custom configurations like 2GB or 512MB, the following option can be added on the defconfig
+according with the customization needed. (Check also the Kconfig file at the mx6dqscm directory)
 
-Here are some examples for some combinations among the different supported options:
+ - memory size option: 512MB, 2GB (if not set any, 1GB is the default value)
 
- - memory size option: 512MB, 1GB, 2GB
- - memeory mode: fix, interleave or single(only for 512MB)
- - boot mode: SPI-NOR boot or SD
- - board: evb, qwks
+     CONFIG_SCM_LPDDR2_512MB
+     CONFIG_SCM_LPDDR2_2GB
 
+ - memeory mode: fix or interleave (if not set any, fix/single mode is the default mode)
 
-512mb qwks-rev2:
-----------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=512,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-512mb-qwks-rev2-ldo.dtb\",SCM_LPDDR2_512MB"
+     CONFIG_INTERLEAVING_MODE
 
+ - boot mode: SPI-NOR boot or SD (if not set any, MMC/SD is the default boot mode)
 
-512mb qwks-rev2 spinor-boot:
-----------------------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=512,SYS_BOOT_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-512mb-qwks-rev2-ldo.dtb\",SCM_LPDDR2_512MB"
+     CONFIG_SPI_BOOT
 
+ - board: evb, qwks (if not set any, qwks-rev2 is the default board)
 
-2gb fix evb:
-------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=2048,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-2gb-evb-fix-ldo.dtb\",SCMEVB,SCM_LPDDR2_2GB"
-
-
-2gb interleaving evb:
----------------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=2048,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-2gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB,SCM_LPDDR2_2GB"
-
-
-2gb interleaving evb spinor-boot:
----------------------------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=2048,SYS_BOOT_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-2gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB,SCM_LPDDR2_2GB"
-
-1gb interleaving evb android:
------------------------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-1gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB,ANDROID_SUPPORT"
-
-
-1gb interleaving qwks_rev2:
----------------------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=1024,SYS_USE_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-1gb-qwks-rev2-interleave-ldo.dtb\",INTERLEAVING_MODE"
-
-
-1gb interleaving evb spinor-boot:
----------------------------------
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg,MX6Q,DDR_MB=1024,SYS_BOOT_SPINOR,DEFAULT_FDT_FILE=\"imx6dqscm-1gb-evb-interleave-ldo.dtb\",INTERLEAVING_MODE,SCMEVB"
+     CONFIG_SCMHVB
+     CONFIG_QWKS_REV3
+     CONFIG_SCMEVB
+     CONFIG_SCMHVB
 
diff --git a/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg b/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg
index d95b9bc..9bf48bd 100644
--- a/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg
+++ b/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg
@@ -1,7 +1,8 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier:     GPL-2.0+
  *
  * Refer docs/README.imxmage for more details about how-to configure
  * and create imximage boot image
@@ -23,9 +24,9 @@ IMAGE_VERSION 2
 
 BOOT_FROM	sd
 
-#ifdef CONFIG_USE_PLUGIN
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
 /*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
-PLUGIN	board/freescale/mx6dscm/plugin.bin 0x00907000
+PLUGIN	board/freescale/mx6dqscm/plugin.bin 0x00907000
 #else
 
 #ifdef CONFIG_SECURE_BOOT
diff --git a/board/freescale/mx6dqscm/mx6dqscm.c b/board/freescale/mx6dqscm/mx6dqscm.c
index de08e95..98f91cc 100644
--- a/board/freescale/mx6dqscm/mx6dqscm.c
+++ b/board/freescale/mx6dqscm/mx6dqscm.c
@@ -1,14 +1,15 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -200,6 +201,7 @@ static iomux_v3_cfg_t const ecspi1_pads[] = {
 static void setup_spi(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+	gpio_request(IMX_GPIO_NR(2, 30), "ECSPI1 CS");
 }
 
 int board_spi_cs_gpio(unsigned bus, unsigned cs)
@@ -238,15 +240,31 @@ static iomux_v3_cfg_t const rgb_pads[] = {
 	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const bl_pads[] = {
 	MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+static void enable_backlight(void)
+{
+	imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));
+	gpio_request(DISP0_PWR_EN, "Display Power Enable");
+	gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
 static void enable_rgb(struct display_info_t const *dev)
 {
 	imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
-	gpio_direction_output(DISP0_PWR_EN, 1);
+	enable_backlight();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	enable_backlight();
 }
 
+#ifdef CONFIG_SYS_I2C
 static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
@@ -259,7 +277,9 @@ static struct i2c_pads_info i2c_pad_info1 = {
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
+#endif
 
+#ifdef CONFIG_PCIE_IMX
 iomux_v3_cfg_t const pcie_pads[] = {
 	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
 	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
@@ -268,7 +288,10 @@ iomux_v3_cfg_t const pcie_pads[] = {
 static void setup_pcie(void)
 {
 	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+	gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");
+	gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");
 }
+#endif
 
 iomux_v3_cfg_t const di0_pads[] = {
 	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	/* DISP0_CLK */
@@ -355,6 +378,7 @@ int board_mmc_init(bd_t *bis)
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
 			gpio_direction_input(USDHC2_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			break;
@@ -362,6 +386,7 @@ int board_mmc_init(bd_t *bis)
 #ifndef CONFIG_SCMHVB
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
 			gpio_direction_input(USDHC3_CD_GPIO);
 #endif
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@@ -388,7 +413,7 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-int mx6_rgmii_rework(struct phy_device *phydev)
+static int mx6_rgmii_rework(struct phy_device *phydev)
 {
 	/* add necessary delays for RGMII,
 	 * there are no board skew delays added
@@ -445,9 +470,6 @@ static void disable_lvds(struct display_info_t const *dev)
 		 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 
 	writel(reg, &iomux->gpr[2]);
-#ifndef CONFIG_SCMEVB
-	gpio_direction_output(DISP0_PWR_EN, 0);
-#endif
 }
 
 static void do_enable_hdmi(struct display_info_t const *dev)
@@ -456,20 +478,6 @@ static void do_enable_hdmi(struct display_info_t const *dev)
 	imx_enable_hdmi_phy();
 }
 
-static void enable_lvds(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)
-				IOMUXC_BASE_ADDR;
-	u32 reg = readl(&iomux->gpr[2]);
-
-	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
-	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
-	writel(reg, &iomux->gpr[2]);
-#ifndef CONFIG_SCMEVB
-	gpio_direction_output(DISP0_PWR_EN, 1);
-#endif
-}
-
 struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
@@ -481,13 +489,13 @@ struct display_info_t const displays[] = {{
 		.refresh        = 60,
 		.xres           = 1024,
 		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
+		.pixclock       = 15384,
+		.left_margin    = 160,
+		.right_margin   = 24,
+		.upper_margin   = 29,
+		.lower_margin   = 3,
+		.hsync_len      = 136,
+		.vsync_len      = 6,
 		.sync           = FB_SYNC_EXT,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
@@ -610,7 +618,6 @@ static void setup_fec(void)
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
-	setup_pcie();
 
 	return cpu_eth_init(bis);
 }
@@ -654,6 +661,8 @@ static void setup_usb(void)
 
 	imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
 					 ARRAY_SIZE(usb_hc1_pads));
+
+	gpio_request(IMX_GPIO_NR(1, 29), "USB HC1 Power Enable");
 }
 
 int board_ehci_hcd_init(int port)
@@ -709,12 +718,19 @@ int board_init(void)
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
+
+#ifdef CONFIG_SYS_I2C
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
 
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif
 
+#ifdef CONFIG_PCIE_IMX
+	setup_pcie();
+#endif
+
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
@@ -725,6 +741,7 @@ int board_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_POWER
 int power_init_board(void)
 {
 	struct pmic *pfuze;
@@ -811,8 +828,98 @@ int power_init_board(void)
 
 	return 0;
 }
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+
+int power_init_board(void)
+{
+	struct udevice *dev;
+	unsigned int reg;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW3A to 1.25V for LPDDR2 */
+	reg = pmic_reg_read(dev, PFUZE100_SW3AVOL);
+	reg &= ~0x3f;
+	reg |= 0x22;
+	pmic_reg_write(dev, PFUZE100_SW3AVOL, reg);
+
+	/* set SW2 to 3.2V */
+	reg = pmic_reg_read(dev, PFUZE100_SW2VOL);
+	reg &= ~0x7f;
+	reg |= 0x72;
+	pmic_reg_write(dev, PFUZE100_SW2VOL, reg);
+
+	/* set VGEN1 to 1.5V */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN1VOL);
+	reg &= ~0x0f;
+	reg |= 0x0e;
+	pmic_reg_write(dev, PFUZE100_VGEN1VOL, reg);
+
+	/* set VGEN3 to 2.8V */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
+	reg &= ~0x0f;
+	reg |= 0x0a;
+	pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
+
+	/* set VGEN4 to 2.5V */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN4VOL);
+	reg &= ~0x0f;
+	reg |= 0x07;
+	pmic_reg_write(dev, PFUZE100_VGEN4VOL, reg);
+
+	/* set VGEN5 to 3.3V */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+	reg &= ~0x0f;
+#ifdef CONFIG_QWKS_REV3
+	reg |= 0x07;
+#else
+	reg |= 0x0f;
+#endif
+	pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+
+	/* set VGEN6 to 3.2V */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN6VOL);
+	reg &= ~0x0f;
+	reg |= 0x0e;
+	pmic_reg_write(dev, PFUZE100_VGEN6VOL, reg);
+
+	/* set SW1AB staby volatage 0.975V*/
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+	/* set SW1C staby volatage 0.975V*/
+	reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+#endif
 
 #ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER
 void ldo_mode_set(int ldo_bypass)
 {
 	unsigned int value;
@@ -885,6 +992,61 @@ void ldo_mode_set(int ldo_bypass)
 		printf("switch to ldo_bypass mode!\n");
 	}
 }
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+	int is_400M;
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pfuze100", &dev);
+
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+		/* increase VDDARM to 1.425V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
+
+		/* increase VDDSOC to 1.425V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
+	}
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+
+		/* decrease VDDARM for 400Mhz DQ:1.1V */
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);
+
+		/* increase VDDSOC to 1.3V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x28);
+
+		/*
+		 * MX6Q:
+		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+		 */
+		is_400M = set_anatop_bypass(2);
+
+		if (is_400M)
+			pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x1b);
+		else
+			pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x22);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
 #endif
 
 #ifdef CONFIG_CMD_BMODE
@@ -983,6 +1145,7 @@ int check_recovery_cmd_file(void)
 	imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
 					 ARRAY_SIZE(recovery_key_pads));
 
+	gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key");
 	gpio_direction_input(GPIO_VOL_DN_KEY);
 
 	if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN is low assert */
diff --git a/board/freescale/mx6dqscm/plugin.S b/board/freescale/mx6dqscm/plugin.S
index bd4f542..f604e97 100644
--- a/board/freescale/mx6dqscm/plugin.S
+++ b/board/freescale/mx6dqscm/plugin.S
@@ -1,7 +1,8 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <config.h>