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author | Alison Wang <b18965@freescale.com> | 2015-06-09 16:07:49 +0800 |
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committer | York Sun <yorksun@freescale.com> | 2015-07-20 11:44:38 -0700 |
commit | 88c857df8cf4956195b10afbbe08cc3912d45429 (patch) | |
tree | a9e4d28145555e1c297ded0fb935eca41ed5a818 /board | |
parent | 340848b1853fde95991cb76fee78a69eafd83335 (diff) | |
download | u-boot-imx-88c857df8cf4956195b10afbbe08cc3912d45429.zip u-boot-imx-88c857df8cf4956195b10afbbe08cc3912d45429.tar.gz u-boot-imx-88c857df8cf4956195b10afbbe08cc3912d45429.tar.bz2 |
arm/ls102xa: Add little-endian mode support for audio IPs
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board')
-rw-r--r-- | board/freescale/ls1021aqds/ls1021aqds.c | 3 | ||||
-rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 92f613a..ce5cb52 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -209,6 +209,9 @@ int board_early_init_f(void) out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 043d938..8fef8e9 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -368,6 +368,9 @@ int board_early_init_f(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) |